• KIISE Transactions on Computing Practices
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• v.21 no.12
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• pp.745-750
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• 2015

LiDAR(Light Detection and Ranging) technology provides realistic 3-dimension image information, and it has been widely utilized in various fields. However, the utilization of this technology in the military domain requires prompt responses to dynamically changing tactical environment and is therefore limited since LiDAR technology requires complex processing in order for extensive amounts of LiDAR data to be utilized. In this paper, we introduce an Unmanned Aircraft Platform Based Real-time LiDAR Data Processing Architecture that can provide real-time detection information by parallel processing and off-loading between the UAV processing and high-performance data processing areas. We also conducted experiments to verify the feasibility of our proposed architecture. Processing with ARM cluster similar to the UAV platform processing area results in similar or better performance when compared to the current method. We determined that our proposed architecture can be utilized in the military domain for tactical and combat purposes such as unmanned monitoring system.

• Journal of KIISE
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• v.41 no.9
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• pp.605-610
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• 2014

Now, virtualization is no more emerging research area, and we can easily find its application in our circumstance. Nevertheless, I/O workloads are reluctant to be applied in virtual environment since they still suffer from unacceptable performance degradation due to virtualization latency. Many previous papers identified that virtual I/O overhead is mainly caused by exits and redundant I/O stack, and proposed several techniques to reduce them. However, they still have some limitations. In this paper, we introduce a novel I/O virtualization framework which improves I/O performance by exploiting multicore architecture. We applied our framework to the virtual network, and it improves TCP throughput up to 169%, and decreases UDP latency up to 38% on the network with the 10Gbps NIC.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.24 no.4
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• pp.33-42
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• 2010

The induction motor drive applied to field oriented control is widely used in industry applications. However, it is deceased performance and authenticity by saturation, temperature changing, disturbance and parameters changing because modeling of induction motor is nonlinear and complex. In order to control variable speed operation, conventional PI-like controllers are commonly used. These controllers provide limited good performance over a wide range of operation, even under ideal field oriented conditions. This paper proposes self tuning PI controller based on fuzzy-neural network(FNN)-PI controller that is implemented using fuzzy control, neural network, and adaptive fuzzy controller(AFC). Also, this paper proposes estimation of speed using ANN. The proposed control algorithm is applied to induction motor drive system using FNN-PI, AFC and ANN controller. Also, this paper proposes the anlysis results to verify the effectiveness of controller.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.12
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• pp.2333-2340
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• 2016

A LEA (Lightweight Encryption Algorithm) crypto-processor was designed, which supports three master key lengths of 128/ 192/256-bit, ECB and CTR modes of operation. To achieve high throughput rate, the round transformation block was designed with 128 bits datapath and a pipelined structure of 16 stages. Encryption/decryption is carried out through 12/14/16 pipelined stages according to the master key length, and each pipelined stage performs round transformation twice. The key scheduler block was optimized to share hardware resources that are required for encryption, decryption, and three master key lengths. The round keys generated by key scheduler are stored in 32 round key registers, and are repeatedly used in round transformation until master key is updated. The pipelined LEA processor was verified by FPGA implementation, and the estimated performance is about 8.3 Gbps at the maximum clock frequency of 130 MHz.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.38 no.5
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• pp.58-64
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• 2001

Recently many informations are transmitted ,md stored as video data, and they are on the rapid increase because of popularization of high performance computer and internet. In this paper, to retrieve video data, shots are found through analysis of video stream and the method of detection of key frame is studied. Finally users can retrieve the video efficiently. This Paper suggests a new feature that is robust to object movement in a shot and is not sensitive to change of color in boundary detection of shots, and proposes the characterizing value that reflects the characteristic of kind of video (movie, drama, news, music video etc,). The key frames are pulled out from many frames by using the local minima and maxima of differential of the value. After original frame(not de image) are reconstructed for key frame, indexing process is performed through computing parameters. Key frames that arc similar to user's query image arc retrieved through computing parameters. It is proved that the proposed methods are better than conventional method from experiments. The retrieval accuracy rate is so high in experiments.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.85-95
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• 2008

Characteristically, 3D graphic algorithms have to perform complex calculations on massive amount of stream data. The vertex and pixel shaders have enabled efficient execution of graphic algorithms by hardware, and these graphic processors may seem to have achieved the aim of "hardwarization of software shaders." However, the hardware shaders have hitherto been evolving within the limits of Z-buffer based algorithms. We predict that the ultimate model for future graphic processors will be an algorithm-independent integrated shader which combines the functions of both vertex and pixel shaders. We design the register file model that supports 3-dimensional computer graphic on the programmable unified shader processor. we have verified the accurate calculated value using FPGA Virtex-4(xcvlx200) made by Xilinx for operating binary files made by the implementation progress based on synthesis results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.54-60
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• 2008

The bus architecture consists of a master initiating a communication transaction, a slave responding to the transaction, a arbiter selecting a master, a bridge connecting buses and so on. Recently this is more complicated and developed toward multi-bus architecture. In this paper, several cases of multi-shared bus architecture are discussed and in order to decrease the bridge latency, the architecture introducing a memory selector is proposed. Finally, a LCD controller using DMA master is integrated in this bus architecture that is verified due to RTL simulation and FPGA board test. DMA, LCD line buffer and SDRAM controller are normally operated in the timing simulation using ModelSim tool, and the LCD image is confirmed in the real FPGA board containing LCD panel.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.24-31
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• 2008

Power converters are becoming an essential block in modem mobile multimedia application. This paper presents a high performance DC-DC buck converter for mobile applications. Controller of DC-DC buck converter is designed by current-mode control method. An current-mode DC-DC converter is implemented in a standard $0.18{\mu}m$ CMOS process, and the overall die size was $1.2mm^2$. The peak efficiency was 86 % with a switching frequency of $1\sim1.5MHz$ and a maximum load current of 400mA.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.2
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• pp.23-29
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• 2014

The advanced traffic management system of intelligent transport systems automates the related traffic tasks such as vehicle speed, traffic volume and traffic incidents through the improved infrastructures like high definition cameras, high-performance radar sensors. For the safety of road users, especially, the automated incident detection and secondary accident prevention system is required. Normally, CCTV based image object detection and radar based object detection is used in this system. In this paper, we proposed the algorithm for real time highway incident detection system using multi surveillance cameras to mosaic video and track accurately the moving object that taken from different angles by background modeling. We confirmed through experiments that the video detection can supplement the short-range shaded area and the long-range detection limit of radar. In addition, the video detection has better classification features in daytime detection excluding the bad weather condition.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.149-155
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• 2012

SSD is a storage device of having high-performance controller and cache buffer and consists of many NAND flash memories. Because NAND flash memory does not support in-place update, valid pages are invalidated when update and erase operations are issued in file system and then invalid pages are completely deleted via garbage collection. However, garbage collection performs many erase operations of long latency and then it reduces I/O performance and increases wear leveling in SSD. In this paper, we propose a new method of de-duplicating valid data and recycling invalid data. The method de-duplicates valid data and then recycles invalid data so that it improves de-duplication ratio. Due to reducing number of writes and garbage collection, the method could increase I/O performance and decrease wear leveling in SSD. Experimental result shows that it can reduce maximum 20% number of garbage collections and 9% I/O latency than those of general case.