• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.12 no.4
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• pp.81-89
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• 1998

In the field of industrial drives, the vector control of the induction motor has been widely used to achieve the good control performance. In this paper, to require the information of rotor flux in direct vector control scheme, the flux observer by current model of rotor circuit is used. This flux observer is not only available at low-speed region bt good for the error reduction by feedback properties. Also, employing the flux observer on rotor reference frame, the robustness of decoupling control to the observation of rotor flux can be achieved. Through digital simulation and DSP-based IGBT inverter system, the validity for practical implementation is verified.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2006.05a
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• pp.315-320
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• 2006

This paper presents speed control of IPMSM drive using neural network(NN) PI controller. In general, PI controller in computer numerically controlled machine process fixed gain. They may perform well under some operating conditions, but not all. To increase the robustness of fixed gain PI controller, NNPI controller proposes a new method based neural network. NNPI controller is developed to minimize overshoot, rise time and settling time following sudden parameter changes such as speed, load torque and inertia. Also, this paper is proposed speed control of IPMSM using neural network and estimation of speed using artificial neural network(ANN) controller. The back propagation neural network technique is used to provide a real time adaptive estimation of the motor speed. The results on a speed controller of IPMSM are presented to show the effectiveness of the proposed gain tuner. And this controller is better than the fired gains one in terms of robustness, even under great variations of operating conditions and load disturbance.

• Journal of KIISE:Computing Practices and Letters
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• v.11 no.6
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• pp.477-487
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• 2005

As embedded system grows in size and complexity, the importance of the technique for dynamic memory allocation has increased. The objective of this paper is to measure the performance of dynamic memory allocation by varying both hardware and software design parameters for embedded systems. Unlike torrent performance evaluation studies that have presumed the single threaded system with single address spate without OS support, our study adopts realistic environment where the embedded system runs on Linux OS. This paper contains the experimental performance analyses of dynamic memory allocation method by investigating the effects of each software layer and some hardware design parameters. Our quantitative results tan be used to help system designers design high performance, low power embedded systems.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.9
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• pp.461-468
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• 2001

Though shared virtual memory (SVM) system promise low cost solutions for high performance computing they suffer from long memory latencies. These latencies are usually caused by repetitive invalidations on shared data. Since shared data are accessed through synchronization and the patterns by which threads synchronizes are repetitive, a prefetching scheme bases on such repetitiveness would reduce memory latencies. Based on this observation, we propose a prefetching technique which predicts future access behavior by analyzing access history per synchronization variable. Our technique was evaluated on an 8-node SVM system using the SPLASH-2 benchmark. The results show the our technique could achieve 34%~45% reduction in memory access latencies.

• Journal of Broadcast Engineering
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• v.24 no.1
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• pp.182-185
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• 2019

This paper analyzes performances of modules in implementing a programmable multi-format video decoder. The goal of the proposed platform is the high-end Full High Definition (FHD) video decoder. The proposed multi-format video decoder consists of a reconfigurable processor, dedicated bit-stream co-processor, memory controller, cache for motion compensation, and flexible hardware accelerators. The experiments suggest performance baseline of modules for the proposed architecture operating at 300 MHz clock with capability of decoding HEVC bit-streams of FHD 30 frames per second.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.4
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• pp.1-8
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• 2004

A novol clock distribution scheme is proposed for high-speed and low-power digital system to minimize clock skew and reduce dynamic power consumption. This scheme has ideal zero-skew characteristic by using folded clock lines (FCL) and phase blending circuit. For analyzing suitable line structures to FCLs, microstrip line and coplanar line are placed with folded clock lines. Simulation results show that the maximum clock-skew between two receivers located 10mm apart is less than lops at 1㎓ and the maximum clock-skew between two receivers located 20mm apart is less than 60ps at 1㎓. Also the results show that the minimum skews of clock signals regardless of process, voltage, and temperature variation are invariant.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.112-120
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• 2013

In this paper, we propose high-performance H.264/AVC CAVLC encoder for UD video real time processing. Statistical values are obtained in one cycle through the parallel arithmetic and logical operations, using non-zero bit stream which represents zero coefficient or non-zero coefficient. To encode codeword per one cycle, we remove recursive operation in level encoding through parallel comparison for coefficient and escape value. In oder to implement high-speed circuit, proposed CAVLC encoder is designed in two-stage {statical scan, codeword encoding} pipeline. Reducing the encoding table, the arithmetic unit is used to encode non-coefficient and to calculate the codeword. The proposed architecture was simulated in 0.13um standard cell library. The gate count is 33.4Kgates. The architecture can support Ultra Definition Video ($3840{\times}2160$) at 100 frames per second by running at 100MHz.

• Journal of the Korean Chemical Society
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• v.53 no.6
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• pp.742-748
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• 2009

In the meat industry, correct breed information in food labeling is required to assure meat quality. Genetic markers provide corroborating evidence to identify breed. We described the development of DNA markers to discriminate between Korean beef cattle (Hanwoo), Holstein, and mixed cow beefs. As most breeds are standardized for coat colour, the melanocortin 1 receptor (MC1R) gene, involved in the regulation of eu/pheomelanins synthesis, has been suggested as marker for breed traceability of products of animal origin. We also designed sex-determining region Y (SRY) gene specific primers for Y chromosome detection. In this study, fragments of MC1R gene and SRY gene were amplified by multiplex-PCR and subjected to digestion by MspA1I restriction endonuclease. Reaction products were analysised by denaturing high performance liquid chromatography (DHPLC). As a result, we identified 6 DHPLC peak types from MC1R gene and SRY gene analysis. DHPLC method showed more sensitive than RFLP method for DNA fragments analysis. Therefore, DHPLC method can apply to identify for Hanwoo, Holstein and mixed beef.

• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.2
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• pp.285-290
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• 2023

Compressors are widely used in high-speed electronic systems and are used to reduce the number of operands in multiplier. The proposed compressor is constructed based on the m-GDI(: modified gate diffusion input) to reduce the propagation delay time. This paper is compared the performance of compressors by applying 4-2, 5-2 and 6-2 m-GDI compressors to the multiplier, respectively. As a simulation results, compared to the 8-bit Dadda multiplier using the 4-2 and 6-2 compressor, the multiplier using the 5-2 compressor is reduced propagation delay time 13.99% and 16.26%, respectively. Also, the multiplier using the 5-2 compressor is reduced PDP(: Power Delay Product) 4.99%, 28.95% compared to 4-2 and 6-2 compressor, respectively. However, the multiplier using the 5-2 compression circuit is increased power consumption by 10.46% compared to the multiplier using the 4-2 compression circuit. In conclusion, the 8-bit Dadda multiplier using the 5-2 compressor is superior to the multipliers using the 4-2 and 6-2 compressors. The proposed circuit is implemented using TSMC 65nm CMOS process and its feasibility is verified through SPECTRE simulation.

• Journal of KIISE
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• v.43 no.5
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• pp.524-530
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• 2016

The desire to access data faster and the growth of next-generation memories such as non-volatile memories, contribute to the development of research on memory file systems. It is recommended that memory mapped file I/O, which has less overhead than read-write I/O, is utilized in a high-performance memory file system. Memory mapped file I/O, however, brings a page table overhead, which becomes one of the big overheads that needs to be resolved in the entire file I/O performance. We find that same overheads occur unnecessarily, because a page table of a file is removed whenever a file is opened after being closed. To remove the duplicated overhead, we propose the mapping cache, a technique that does not delete a page table of a file but saves the page table to be reused when the mapping of the file is released. We demonstrate that mapping cache improves the performance of traditional file I/O by 2.8x and web server performance by 12%.