• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.6
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• pp.43-51
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• 2004

An optical parallel modified signed-digit(MSD) number adder system is proposed by using triple rail-coding input patterns and serial arrangement method of symbolic substitution. By combing overlapped arithmetic results. which are produced by encoding MSD input as triple rail-coding patterns. into the same patterns, symbolic substitution rules are reduced and also by using serialized and space-shifted input patterns in optical experiments, the optical adder without space-shifting operation, NOR operation and threshold operation is implemented.

• Communications of Mathematical Education
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• v.25 no.3
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• pp.525-536
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• 2011

In the College Scholastic Ability Test, applicants of science tracks usually choose type Ga mathematics. However, students who took type Na mathematics test can also apply to science and engineering tracks in many universities by cross-Applications. Many universities have given additional points to type Ga mathematics test taker in order to recruit students who excel in the natural science track curriculum. In this paper, we study the necessity and effect of additional points system by using the data of Seoul National University of Science and Technology.

• The Korean Journal of Applied Statistics
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• v.27 no.6
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• pp.923-932
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• 2014

The Hurdle model can to analyze zero-inflated count data. This model is a mixed model of the logit model for a binary component and a truncated Poisson model of a truncated count component. We propose a new hurdle model with a general heterogeneous random effects covariance matrix to analyze longitudinal zero-inflated count data using modified Cholesky decomposition. This decomposition factors the random effects covariance matrix into generalized autoregressive parameters and innovation variance. The parameters are modeled using (generalized) linear models and estimated with a Bayesian method. We use these methods to carefully analyze a real dataset.

• Journal of IKEEE
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• v.7 no.1 s.12
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• pp.56-62
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• 2003

In this paper, we designed a adder and a multiplier using current mode T-gate on $GF(2^2)$. The T-gate is consisted of current mirror and pass transistor, the designed 4-valued T-gate used adder and multiplier on $GF(2^2)$. We designed its under 1.5um CMOS standard technology. The unit current of the circuits is 15㎂, and power supply is 3.3V VDD. The proposed current mode CMOS operator have a advantage of module by T-gate`s arrangement, and so we easily implement multi-valued operator.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.3
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• pp.439-446
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• 1998

This paper presents design of SD adder and PD adder on Multi-Valued Logic. For implementing of Multi-valued logic circuits we use Current-mode CMOS circuits and also use Voltage-mode CMOS circuits partially. The proposed arithmetic circuits was estimated by SPICE simulation. At the SD(Signed-Digit) number presentation applying Multi-Valued logic the carry propagation is always limited to one position to the left this number presentation allows fast parallel operation. The addition method that add M operands using PD( positive digit number) is effective not only for the realization of the high-speed compact arithmetic circuit, but also for the reduction of the interconnection in the VLSI processor. therefor, if we use PD number representation, the high speed processor can be implementation.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.8
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• pp.35-45
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• 1999

In this paper, the addition and the multiplicative algorithm of two polynomials over finite field $GF(p^m)$ are presented. The 4-valued arithmetic processor of the serial input-parallel output modular structure on $GF(4^3)$ to be performed the presented algorithm is implemented by current mode CMOS. This 4-valued arithmetic processor using current mode CMOS is implemented one addition/multiplication selection circuit and three operation circuits; mod(4) multiplicative operation circuit, MOD operation circuit made by two mod(4) addition operation circuits, and primitive irreducible polynomial operation circuit to be performing same operation as mod(4) multiplicative operation circuit. These operation circuits are simulated under $2{\mu}m$ CMOS standard technology, $15{\mu}A$ unit current, and 3.3V VDD voltage using PSpice. The simulation results have shown the satisfying current characteristics. The presented 4-valued arithmetic processor using current mode CMOS is simple and regular for wire routing and possesses the property of modularity. Also, it is expansible for the addition and the multiplication of two polynomials on finite field increasing the degree m and suitable for VLSI implementation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.10a
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• pp.499-503
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• 2000

The use of Multiple-Valued FFT(Fast fourier Transform) is extended from binary to multiple-valued logic(MVL) circuits. A multiple-valued FFT circuit can be implemented using current-mode CMOS techniques, reducing the transitor, wires count between devices to half compared to that of a binary implementation. For adder processing in FFT, We give the number representation using such redundant digit sets are called redundant positive-digit number representation and a Redundant set uses the carry-propagation-free addition method. As the designed Multiple-valued FFT internally using PD(positive digit) adder with the digit set 0,1,2,3 has attractive features on speed, regularity of the structure and reduced complexities of active elements and interconnections. for the mutiplier processing, we give Multiple-valued LUT(Look up table)to facilitate simple mathmatical operations on the stored digits. Finally, Multiple-valued 8point FFT operation is used as an example in this paper to illuatrates how a multiple-valued FFT can be beneficial.

• Proceedings of the Acoustical Society of Korea Conference
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• spring
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• pp.47-50
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• 2000

비상관적인 가산잡음에 오염된 음성으로부터 향상된 음성을 얻기 위한 방법 중 Soft Decision에 근거한 음성 향상 기법이 뛰어난 성능을 가진다고 알려져 있다. Soft Decision은 주파수 영역에서 음성에 가산된 잡음을 처리하며, 잡음 환경에 대한 사전정보에 의존적이다. 본 연구에서는 Soft Decision을 근거로 음성에 가산된 잡음신호를 비선형 처리를 하여 효과적으로 음성에 포함된 잡음을 추정하도록 하였으며, 잡음환경에 대한 사전 정보 없이 효율적으로 잡음을 억제하는 방법을 제안한다. 본 연구에서 제안한 음성향상 기법은 주관적인 음질평가에서 기존의 방법들보다 나은 성능을 나타내었다

• Information and Communications Magazine
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• v.33 no.9
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• pp.17-23
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• 2016

실세계 환경의 원거리에서 녹음된 음성은 가산 잡음이나 반향 성분으로 왜곡되기 때문에 음성인식 성능이 현저히 떨어진다. 따라서 음성 전처리 과정은 실세계 환경에서 강인한 음성인식을 위한 필수과정이다. 모델 기반 특징 향상 방법은 전처리 방법 중 하나로 특징 영역 데이터의 적절한 동적 범위(dynamic range)와 차원 수로 인하여 실시간 처리가 가능하고 깨끗한 음성의 선험적 정보를 모델링하기에 용이하다. 또, 인식을 위한 최종 특징 입력에 가까운 단계에서 데이터를 처리하므로 인식에 밀접한 영향을 준다는 장점이 있다. 그러나 대략적인 왜곡 요인 관련 파라미터 추정 때문에 음성인식 성능이 하락되는 단점이 있다. 최근에 기존 모델 기반 특징 향상의 단점을 개선하여 가산 잡음이나 반향 환경에 적합한 방법이 제안되었다. 이글에서는 특징 향상 방법을 소개하고 개선된 방법의 음성인식 강인성을 알아보고자 한다.

• 월간 기계설비
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• no.9 s.218
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• pp.43-50
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• 2008

고도로 발전하고 있는 건설산업과 소비자의 요구가 점차 세분화 되면서 객관적인 평가기능을 갖추고 있는 품질경영시스템이 지난 1992년부터 건설업계에 도입됨에 따라 건설업계는 시공의 표준화가 정착되어 가는 중이다. 최근에는 환경 및 안전.보건에 대한 관심이 높아지면서 건설업계는 환경.안전보건경영시스템 획득으로 기업경영의 우수성을 객관적으로 인증 받는 추세이다. 설비건설업계의 경우 환경경영시스템(ISO 14001)을 인증 받은 업체가 36개사, 안전보건경영시스템(K-OHSMS 18001)은 2개사, 안전경영시스템(KOSHA 18001, 건설업)은 3개사가 인증을 받는 등 아직 초기단계에 있으나 점차 확대될 전망이다. 환경.안전보건경영시스템을 인증 받을 경우 금융기관의 기술신용평가시 가산점 부여, 시공능력평가시 가산점 부여, 기술비 세액공제, 인증획득 자금지원, 융자신청시 가산점 부여, 기업실무자 교육비지원 등의 혜택이 주어지나, 무엇보다도 지속적인 관리로 업무의 질적 향상과 체계적인 관리를 통해 한 단계 업그레이드 가능한 것을 장점으로 꼽을 수 있다. 본지는 환경·안전보건경영시스템 인증 절차 및 인증시 효과에 대해 알아본다.