• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.7
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• pp.530-532
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• 1999

A new lateral device entitled SB-DCEST(segmented p-base dual-channel emitter switched thyristor), which suppresses the snapback is proposed and successfully fabricated. The proposed device effectively suppressed the snapback phenomenon by employing the gigh resistance in self-aligned segmented p-base when compared with the conventional DCEST. The experimental results show that the SB-DCEST has the low forward voltage drop of 4.3 V at anode current of $150 A/cm^2$ with the eliminated snap-back regime, while conventional DCEST exhibits higher forward voltage drop of 5.3 V.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.7
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• pp.88-93
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• 1998

For the self-aligned AlGaAs/GaAs HBTs, the surface states at the interface between the extrinsic base surface and the passivation nitride is a major cause of degradation of dc characteristics. In this paper the degradation mechanisms of self-aligned AlGaAs/GaAs HBT were analyzed, and GaAs HBTs, which employed an InGaP ledge emitter structure formed by the nonself-aligned process to cover the surface of the extrinsic base and reduce the surface states, produced high reliability. Accoridng to the acceleration lifetime test, the nonself-aligned InGaP/GaAs HBTs produced very reliable dc characteristics comparing with the self-aligned AlGaAs/GaAs HBTs. The activation energy was 1.97eV and MTTF $4.8{\times}10^{8}$ hrs at $140^{\circ}C$ which satisfied the MIL standard.

• Journal of the Korean Society of Safety
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• v.28 no.2
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• pp.26-30
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• 2013

The purpose of this study is to find risk factors by analyzing the operation principle of a photo coupler (P/C) used to remove the noise of electronic devices and establish a base for the performance improvement of developed products. It was found from the P/C circuit analysis of normal products that they were equipped with an electrolytic condenser of $0.1{\mu}F$ to smooth system signals. Due to the epoxy resin packing the external part of the P/C, this study experienced a limit to visually examine the damage to it. It could be seen from the analysis of electric characteristics of the P/C that the forward voltage ($V_f$) and reverse current ($I_r$) were 1.3 V and 10 uA, respectively. In addition, it is required that the breakdown voltage (VCE) between the collector (C) and emitter (E) be maintained at less than 35 V. The and of the damaged product #1 were comparatively good. However, the measurement of was 100.0 uA. From this, it is thought that a short circuit occurred to the internal circuit. Moreover, from the fact that the of the damaged product #2 was open circuit and the measurement of was 0.0 uA, it is thought that the collector and emitter was separated or insulation resistance was significantly high. Furthermore, from the fact that the of the damaged product #3 was open circuit and the measurement of was 0.0 uA, it is thought that the space between the collector (C) and emitter (E) failed to meet the design standard or that they were separated. Therefore, it is thought that fabricating the P/C by increasing the reverse current 10 mA to 50 mA will prevent its malfunction.

• Current Applied Physics
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• v.18 no.11
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• pp.1268-1274
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• 2018

We have investigated the effects of chemical rounding (CR) on the surface passivation and/or antireflection performance of $AlO_{x^-}$ and $AlO_x/SiN_x:H$ stack-passivated pyramid textured $p^+$-emitters with two different boron doping concentrations, and on the performance of bifacial n-PERT Si solar cells with a front pyramid textured $p^+$-emitter. From experimental results, we found that chemical rounding markedly enhances the passivation performance of $AlO_x$ layers on pyramid textured $p^+$-emitters, and the level of performance enhancement strongly depends on boron doping concentration. Meanwhile, chemical rounding increases solar-weighted reflectance ($R_{SW}$) from ~2.5 to ~3.7% for the $AlO_x/SiN_x:H$ stack-passivated pyramid textured $p^+$-emitters after 200-sec chemical rounding. Consequently, compared to non-rounded bifacial n-PERT Si cells, the short circuit current density Jsc of 200-sec-rounded bifacial n-PERT Si cells with ~60 and ${\sim}100{\Omega}/sq$ $p^+$-emitters is reduced by 0.8 and $0.6mA/cm^2$, respectively under front $p^+$-emitter side illumination. However, the loss in the short circuit current density Jsc is fully offset by the increased fill factor FF by 0.8 and 1.5% for the 200-sec-rounded cells with ~60 and ${\im}100{\Omega}/sq$ $p^+$-emitters, respectively. In particular, the cell efficiency of the 200-sec-rounded cells with a ${\sim}100{\Omega}/sq$ $p^+$-emitter is enhanced as a result, compared to that of the non-rounded cells. Based on our results, it could be expected that the cell efficiency of bifacial n-PERT Si cells would be improved without additional complicated and costly processes if chemical rounding and boron doping processes can be properly optimized.

• 한국신재생에너지학회:학술대회논문집
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• 2011.05a
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• pp.123.2-123.2
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• 2011

$ALU^+$ 태양전지는 PN접합을 후면에서 즉, Al을 소성하여 형성시키기 때문에 얼마나 균일하고 두껍게 형성하는 것이 가장 중요하다. 소성(Firing)은 태양전지 제조 과정에서 후면의 접촉을 위한 중요한 공정이다. 본 연구에서는 상업화가 가능한 n-type $ALU^+$ Emitter 태양전지에서 소성 횟수에 따른 특성을 연구 하였다. $ALU^+$ emitter 형성의 최적화를 위해 소성온도를 가변하고, 최적화된 온도에서 소성 횟수에 따른 DIV 측정을 통해 셀을 분석 하였다. 소성 횟수는 1~3회로 하였고, 그 결과 단락전류 밀도(Jsc)가 33.57mA/$cm^2$로 처음보다 15.1%증가 하였고, 곡선인자(Fill Factor)는 3회에서 66.04%로 218%증가 하였다. Al을 짧은 시간 안에 소성을 시키므로 해서 후면의 $P^+$ Emitter가 균일하게 형성되었기 때문에 개방전압(Voc)의 증가를 확인하였다. 본 연구를 통해 $ALU^+$ 태양전지의 후면 Aluminium 소성 조건의 최적화를 통하여 $ALU^+$ emitter가 충분히 형성되지 못하면 누설전류가 발생되고 직렬저항(Rs)이 크게 증가하여 개방전압(Voc) 및 단락전류밀도(Jsc)의 감소가 발생하게 되고, 직렬저항(Rs)의 증가와 병렬저항(Rsh)의 감소는 Fill Factor의 급격한 감소를 초래하게 됨을 알 수 있다. 이를 개선하면 태양전지 효율을 상승시키는 결과를 얻을 수 있음을 확인하였다.

• The Korean Journal of Ceramics
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• v.2 no.4
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• pp.193-196
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• 1996

A new type of electron emitter device of chemical-vapor-deposited diamond thin film is proposed. The device is a diode of metal-insulator-insulator-semiconductor (MIS) structure consisting of an intrinsic polycrystalline diamond film as the insulator, an aluminium electrode on one side, and hydrogenated diamond surface on the other side as the p-type semconductor with negative electron affinity (NEA). Electrons will be injected and/or excited to the conduction band of intrinsic diamond layer to be emitted from the hydrogenated diamond surface of NEA.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.68-69
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• 2007

To make cost-effective solar cells, We have to use low cost material or make short process time or high temperature process. In solar cells, formation of emitter is basic and important technique according to build-up P-N junction. Diffusion process using spin-on dopants has all of this advantage. In this paper, We investigated n+ emitter formation spin-on dopants to apply crystalline silicon solar cells. We known variation of sheet resistance according to variation of temperature and single-crystalline and multi-crystalline silicon wafer using Honeywell P-8545 phosphorus spin-on dopants. We obtain uniformity of sheet resistance within 3~5% changing RPM of spin coater.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.4
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• pp.631-639
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• 1987

In this paper, we investigate the heavy doping effects theoretically and model the heavy doping parameters as a function of doping concentration. To apply the heavy doping effects to devices, we also analyze n+ -p solar cells in consideration of these effects and investigate the dependence of open circuit voltage on the emitter design parameters. The heavy doping parameters modeled in this paper are in good agreement with experimental results, and the condition of an emitter in the maximum efficiency of solar cells is obtained from the characterization of it.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.5
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• pp.449-454
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• 2002

The use of a thin film of indium between the ITO and the $n^+-lnP$ contact layers for InP/InGaAs HPTs was studied without degrading its excellent optical transmittance properties. $ITO/n^+-lnP$ ohmic contact was successfully achieved by the deposition of indium and annealing. The specific contact resistance of about $6.6{\times}10^{-4}\Omega\textrm{cm}^2$ was measured by use of the transmission line method (TLM). However, as the thermal annealing was just performed to $ITO/n^+-lnP$ contact without the deposition of indium between ITO and $n^+-lnP$, it exhibited Schottky characteristics. In the applications, the DC characteristics of InP/InGaAs HPTs with ITO emitter contacts was compared with those of InP/InGaAs HBTs with the opaque emitter contacts.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.3
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• pp.66-74
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• 1999

InAlGaAs/InGaAs HBTs with the various emitter junction gradings(xf=0.0-1.0) and the modified collector structures (collector- I;n-p-n, collector-II;i-p-n) are simulated and analyzed by HMC (Hybrid Monte Carlo) method in order to find an optimum structure for the shortest transit time. A minimum base transit time($ au$b) of 0.21ps was obtainsed for HBT with the grading layer, which is parabolically graded from $x_f$=1.0 and xf=0.5 at the emitter-base interface. The minimum collector transit time($\tau$c) of 0.31ps was found when the collector was modified by inserting p-p-n layers, because p layer makes it possible to relax the electric field in the i-type collector layer, confining the electrons in the $\Gamma$-valley during transporting across the collector. Thus InAlGaAs/InGaAs HBT in combination with the emitter grading($x_f$=0.5) and the modified collector-III showed the transit times of 0.87 psec and the cut-off frequency (f$\tau$) of 183 GHz.