• 한국재료학회지
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• 제9권12호
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• pp.1245-1251
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• 1999

상변화형 광디스크는 직접 반복기록에 의한 고속기록, 고밀도화가 가능하고 높은 전송속도, 재생신호의 C/N (carrier to noise) 비가 좋은 장점을 가지고 있으나 반복되는 열에너지에 의한 디스크의 변형과 소거도의 저하, 기록 반복성의 저하가 문제가 된다. 이러한 반복성의 저하를 개선하기 위해 적절한 디스크의 구조와 기록막의 상하부에 유전체 보호막인 ZnS-$SiO_2$ 박막층을 삽입하였다. 박막 제조시 많은 실험변수의 제어를 위해 다꾸찌 방법을 통하여 타겟 R.F. Power 200W, 기판 R.F. Power 20W, 아르곤 압력 4mTorr, 전극거리 6cm의 최적조건을 얻을수 있었다. TEM과 XRD분석 결과, 전극거리가 가까워질수록 높은 증착속도로 인하여 미세한 조직구조를 가지고 있으며, 일정거리 이상 가까워지면 막의 morphology에 나쁜 영향을 끼침을 알 수 있었다. 이러한 막의 morphology의 영향으로 투과율이 감소하는 것을 확인할 수 있었다. AFM과 SEM분석에서는 전극거리가 가까워질수록 높은 증착속도로 인하여 morphology에 나쁜 영향을 끼치고 있음을 확인할 수 있었다. 최적조건에서 증착한 박막은 우수한 morphology를 가진 초미세구조의 치밀하고 결함이 없는 박막이었다. 이 박막은 상변화형 광디스크에서 열적 변형을 억제하고, 열전도를 감소시켜 우수한 유전체 보호피막의 역할을 할 수 있다. 그리고, 전극거리가 ZnS결정립의 크기와 증착속도, morphology에 미치는 영향에 대해 고찰하였다.

• 센서학회지
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• 제8권2호
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• pp.115-123
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• 1999

PSG(800nm)/$Si_3N_4$ (150nm)로 구성된 유전체 membrane 윗면에 heater와 감지전극을 등일면상에 동시에 형성하였다. 제작된 소자의 전체 면적은 $3.78{\times}3.78mm^2$이고, diaphragm의 면적은 $1.5{\times}1.5mm^2$이며, 감지막치 면적은 $0.24{\times}0.24mm^2$였다. 그리고 diaphragm내의 열분포 분석을 유한요소법을 이용하여 수행하였으며, 실제로 제작된 소자의 열분포와 비교하였다. 소비전력은 동작온도 $350^{\circ}C$에서 약 85mW였다. Sn 금속막을 상온과 $232^{\circ}C$의 두 가지 기판온도에서 열증착하였고, 이를 $650^{\circ}C$의 산소분위기에서 3시간 열산화함으로써 $SnO_2$ 감지막을 형성하였다. 그리고 이를 SEM과 XRD로 특성을 분석하였다. 제작된 소자에 대해서 온도 및 습도에 대한 감지막의 영향 및 부탄가스에 대한 반응특성도 조사하였다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.200-200
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• 2010

In recent times, metal oxide semiconductors thin films transistor (TFT), such as zinc and indium based oxide TFTs, have attracted considerable attention because of their several advantageous electrical and optical properties. There are many deposition methods for fabrication of ZnO-based materials such as chemical vapor deposition, RF/DC sputtering and pulsed laser deposition. However, these vacuum process require expensive equipment and result in high manufacturing costs. Also, the methods is difficult to fabricate various multicomponent oxide semiconductor. Recently, several groups report solution processed metal oxide TFTs for low cost and non vacuum process. In this study, we have newly developed solution-processed TFTs based on Ti-related multi-component transparent oxide, i. e., InTiO as the active layer. We propose new multicomponent oxide, Titanium indium oxide(TiInO), to fabricate the high performance TFT through the sol-gel method. We investigated the influence of relative compositions of Ti on the electrical properties. Indium nitrate hydrate [$In(NO^3).xH_2O$] and Titanium isobutoxide [$C_{16}H_{36}O_4Ti$] were dissolved in acetylacetone. Then monoethanolamine (MEA) and acetic acid ($CH_3COOH$) were added to the solution. The molar concentration of indium was kept as 0.1 mol concentration and the amount of Ti was varied according to weighting percent (0, 5, 10%). The complex solutions become clear and homogeneous after stirring for 24 hours. Heavily boron (p+) doped Si wafer with 100nm thermally grown $SiO_2$ serve as the gate and gate dielectric of the TFT, respectively. TiInO thin films were deposited using the sol-gel solution by the spin-coating method. After coating, the films annealed in a tube furnace at $500^{\circ}C$ for 1hour under oxygen ambient. The 5% Ti-doped InO TFT had a field-effect mobility $1.15cm^2/V{\cdot}S$, a threshold voltage of 4.73 V, an on/off current ratio grater than $10^7$, and a subthreshold slop of 0.49 V/dec. The 10% Ti-doped InO TFT had a field-effect mobility $1.03\;cm^2/V{\cdot}S$, a threshold voltage of 1.87 V, an on/off current ration grater than $10^7$, and a subthreshold slop of 0.67 V/dec.

• 마이크로전자및패키징학회지
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• 제15권3호
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• pp.47-52
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• 2008

높은 종횡비를 갖는 비아 및 트렌치 상에 절연 막으로서 $SiO_2$를 증착하고 증착 특성 및 막의 특성을 연구하였다. 실리콘 관통 전극에서 절연 막은 전극의 벽면과 그 내부에 충진 된 물질간의 상호 확산 감소와 물질 간 접착, 전기적 절연, 디바이스로의 전기적 누수 차단 등의 역할을 해야 한다. 따라서 이러한 특성을 확인하기 위해 3종의 화학 기상 증착법인 PECVD, PETEOS, ALD을 선정하고 절연 막 증착 후 특성평가를 진행 하였다. 특성평가 항목 중 step coverage는 PECVD : <30%, PETEOS : 45%, ALD : 75%, 표면 거칠기는 PECVD : 27.8 nm, PETEOS : 2.1 nm, ALD : <2.0 nm으로 측정되어 막질의 특성은 ALD가 가장 우수하게 평가 되었으나, 실제 기술의 적용에서 가장 중요한 요소인 증착률에서 ALD는 $18\;\AA/1cycle$로서 $10\;\AA/min$ 이라는 대략적 시간이 소요되어 $5000\;\AA/min$의 증착률을 보인 PETEOS에 비해 매우 낮은 수준으로 최소 $1000\;\AA$ 이상의 두께가 요구되는 절연 막의 적용에는 어려움이 있고, 따라서 PETEOS가 본 연구에서 최적의 recipe라 평가되었다.

• 대한전자공학회논문지TC
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• 제43권12호
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• pp.83-88
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• 2006

본 논문에서는 일반적인 손실매질의 다층구조로 이루어진 마이크로 스트립선로의 손실특성의 개선을 위한 새로운 구조를 제안한다. MIS(도체-부도체-반도체) 구조로 된 전송선로를 해석하기 위하여 기본적으로 특성임피던스와 전파상수의 추출에 기초한 일반적인 특성화 절차가 사용되고, Si와 SiO2층 사이에 0전위를 가진 도체를 일정한 간격의 주기적인 배열로 고안된 새로운 모델의 MIS구조에 대한 유한차분법을 이용한 해석방법이 사용된다. 특히 전송선로에 대한 유전체의 영향을 줄이기 위하여 0전위를 가진 주기적인 결합의 도체로 이루어진 구조가 시간영역의 신호를 통해 시험된다. 다양한 손실률을 가진 불완전 유전체에 따른 전압 및 전류의 크기뿐만 아니라 주파수 의존적인 추출된 전송선로 파라미터와 등가회로 파라미터가 주파수 함수로서 나타내진다. 특히 본 논문에서 제안한 새로운 구조의 불완전 유전체에 대한 전송선로 파라미터가 주파수 함수로 구해진다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2010년도 제39회 하계학술대회 초록집
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• pp.170-170
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• 2010

Thin-film transistors (TFT) have become the key components of electronic and optoelectronic devices. Most conventional thin-film field-effect transistors in display applications use an amorphous or polycrystal Si:H layer as the channel. This silicon layers are opaque in the visible range and severely restrict the amount of light detected by the observer due to its bandgap energy smaller than the visible light. Therefore, Si:H TFT devices reduce the efficiency of light transmittance and brightness. One method to increase the efficiency is to use the transparent oxides for the channel, electrode, and gate insulator. The development of transparent oxides for the components of thin-film field-effect transistors and the room-temperature fabrication with low voltage operations of the devices can offer the flexibility in designing the devices and contribute to the progress of next generation display technologies based on transparent displays and flexible displays. In this thesis, I report on the dc performance of transparent thin-film transistors using amorphous indium tin zinc oxides for an active layer. $SiO_2$ was employed as the gate dielectric oxide. The amorphous indium tin zinc oxides were deposited by RF magnetron sputtering. The carrier concentration of amorphous indium tin zinc oxides was controlled by oxygen pressure in the sputtering ambient. Devices are realized that display a threshold voltage of 4.17V and an on/off ration of ${\sim}10^9$ operated as an n-type enhancement mode with saturation mobility with $15.8\;cm^2/Vs$. In conclusion, the fabrication and characterization of thin-film transistors using amorphous indium tin zinc oxides for an active layer were reported. The devices were fabricated at room temperature by RF magnetron sputtering. The operation of the devices was an n-type enhancement mode with good saturation characteristics.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2010년도 제39회 하계학술대회 초록집
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• pp.287-287
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• 2010

We report a new direct patterning method, called liquid bridge-mediated nanotransfer molding (LB-nTM), for the formation of two- or three-dimensional structures with feature sizes between tens of nanometers and tens of micron over large areas. LB-nTM is based on the direct transfer of various materials from a mold to a substrate via a liquid bridge between them. This procedure can be adopted for automated direct printing machines that generate patterns of functional materials with a wide range of feature sizes on diverse substrates. Arrays of TIPS-PEN TFTs were fabricated on 4" polyethersulfone (PES) substrates by LB-nTM using PDMS molds. An inverted staggered structure was employed in the TFT device fabrication. A 150 nm-thick indium-tin oxide (ITO) gate electrode and a 200 nm-thick SiO2dielectric layer were formed on a PES substrate by sputter deposition. An array of TIPS-PEN patterns (thickness: 60 nm) as active channel layers was fabricated on the substrate by LB-nTM. The nominal channel length of the TIPS-PEN TFT was 10 mm, while the channel width was 135 mm. Finally, the source and drain electrodes of 200 nm-thick Ag were defined on the substrate by LB-nTM. The TIPS-PEN TFTs can endure strenuous bending and are also transparent in the visible range, and therefore potentially useful for flexible and invisible electronics.

• 한국전기전자재료학회논문지
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• 제17권7호
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• pp.713-717
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• 2004

In this study, the etched trench properties including cross-sectional profile, surface roughness, and crystalline defects were investigated depending on the various silicon etching and additive gases, For the case of HBr$He-O_2SiF_4$ trench etching gas mixtures, the excellent trench profile and minimum defects in the silicon trench were achieved. Due to the residual oxide film grown by the additive oxygen gas, which acts as a protective layer during trench etching, the undercut and defects generation in the trench were suppressed. To improve the electrical characteristics of trench gate, the hydrogen annealing process after trench etching was also adopted. Through the hydrogen annealing, the trench corners might be rounded by the silicon atomic migration at the trench corners having high potential. The rounded trench corner can afford to reduce the gate electric field and grow a uniform gate oxide. As a result, dielectric strength and TDDB characteristics of the hydrogen annealed trench gate oxide were remarkably increased compared to the non-hydrogen annealed one.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2015년도 제49회 하계 정기학술대회 초록집
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• pp.142.2-142.2
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• 2015

Plasma etch endpoint detection (EPD) of SiO2 and PR layer is demonstrated by plasma impedance monitoring in this work. Plasma etching process is the core process for making fine pattern devices in semiconductor fabrication, and the etching endpoint detection is one of the essential FDC (Fault Detection and Classification) for yield management and mass production. In general, Optical emission spectrocopy (OES) has been used to detect endpoint because OES can be a simple, non-invasive and real-time plasma monitoring tool. In OES, the trend of a few sensitive wavelengths is traced. However, in case of small-open area etch endpoint detection (ex. contact etch), it is at the boundary of the detection limit because of weak signal intensities of reaction reactants and products. Furthemore, the various materials covering the wafer such as photoresist (PR), dielectric materials, and metals make the analysis of OES signals complicated. In this study, full spectra of optical emission signals were collected and the data were analyzed by a data-mining approach, modified K-means cluster analysis. The K-means cluster analysis is modified suitably to analyze a thousand of wavelength variables from OES. This technique can improve the sensitivity of EPD for small area oxide layer etching processes: about 1.0 % oxide area. This technique is expected to be applied to various plasma monitoring applications including fault detections as well as EPD.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.31-32
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• 2010

In our previous reports [1-3], electron transport for the switching and memory devices using alkyl thiol-tethered Ru-terpyridine complex compounds with metal-insulator-metal crossbar structure has been presented. On the other hand, among organic memory devices, a memory based on the OFET is attractive because of its nondestructive readout and single transistor applications. Several attempts at nonvolatile organic memories involve electrets, which are chargeable dielectrics. However, these devices still do not sufficiently satisfy the criteria demanded in order to compete with other types of memory devices, and the electrets are generally limited to polymer materials. Until now, there is no report on nonvolatile organic electrets using nano-interfaced organic monomer layer as a dielectric material even though the use of organic monomer materials become important for the development of molecularly interfaced memory and logic elements. Furthermore, to increase a retention time for the nonvolatile organic memory device as well as to understand an intrinsic memory property, a molecular design of the organic materials is also getting important issue. In this presentation, we report on the OFET memory device built on a silicon wafer and based on films of pentacene and a SiO2 gate insulator that are separated by organic molecules which act as a gate dielectric. We proposed push-pull organic molecules (PPOM) containing triarylamine asan electron donating group (EDG), thiophene as a spacer, and malononitrile as an electron withdrawing group (EWG). The PPOM were designed to control charge transport by differences of the dihedral angles induced by a steric hindrance effect of side chainswithin the molecules. Therefore, we expect that these PPOM with potential energy barrier can save the charges which are transported to the nano-interface between the semiconductor and organic molecules used as the dielectrics. Finally, we also expect that the charges can be contributed to the memory capacity of the memory OFET device.[4]