• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.785-789
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• 2005

Low temperature deposition of silicon and silicon nitride films by catalytic CVD technique was studied for application to thin film transistors on plastic substrates for flexible AMOLEDs. The substrate temperature initially held at room temperature, and was controlled successfully below $150^{\circ}C$ during the entire deposition process. Amorphous silicon films having good adhesion, good surface morphology and sufficiently low content of atomic hydrogen were obtained and could be successfully crystallized using excimer laser without a prior dehydrogenation step. $SiN_x$ films showed a good refractive index, a high deposition rate, a moderate breakdown field and a dielectric constant. The Cat-CVD silicon and silicon nitride films can be good candidates for fabricating thin films transistors on plastic substrates to drive active-matrix organic light emitting display.

• Korean Journal of Materials Research
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• v.32 no.6
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• pp.293-300
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• 2022

This study investigated a graded-refractive-index (GRIN) coating pattern capable of improving the light extraction efficiency of GaN light-emitting diodes (LEDs). The planar LEDs had total internal reflection thanks to the large difference in refractive index between the LED semiconductor and the surrounding medium (air). The main goal of this paper was to reduce the trapped light inside the LED by controlling the refractive index using various compositions of (TiO₂)_x(SiO₂)_1-x in GRIN LEDs consisting of five dielectric layers. Several types of multilayer LEDs were simulated and it was determined the transmittance value of the LEDs with many layers was greater than the LEDs with less layers. Then, the specific ranges of incident angles of the individual layers which depend on the refractive index were evaluated. According to theoretical calculations, the light extraction efficiency (LEE) of the five-layer GRIN is 25.29 %, 28.54 % and 30.22 %, respectively. Consequently, the five-layer GRIN LEDs patterned enhancement outcome LEE over the reference planar LEDs. The results suggest the increased light extraction efficiency is related to the loss of Fresnel transmission and the release of the light mode trapped inside the LED chip by the graded-refractive-index.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.169-170
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• 2006

In this study, ultra thin films of ferroelectric vinylidene fluoride-trifluoroethylene (VF2-TrFE) copolymer were fabricated on degenerated Si (n+, $0.002\;{\Omega}{\cdot}cm$) using by spin coating method. A 1~5 wt% diluted solution of purified vinylidene fluoride-trifluoroethylene (VF2:TrFE=70:30) in a dimethylformamide (DMF) solvent were prepared and deposited on silicon wafers at a spin rate of 2000~5000rpm for 30 seconds. After annealing in a vacuum ambient at $200^{\circ}C$ for 60 min, upper gold electrodes were deposited by vacuum evaporation for electrical measurement. X-ray diffraction results showed that the VF2-TrFE films on Si substrates had $\beta$-phase of copolymer structures. The capacitance on $n^+$-Si(100) wafer showed hysteresis behavior like a butterfly shape and this result indicates clearly that the dielectric films have ferroelectric properties. The typical measured remnant polarization (2Pr) and coercive filed (EC) values measured using a computer controlled a RT-66A standardized ferroelectric test system (Radiant Technologies) were about $0.54\;C/cm^2$ and 172 kV/cm, respectively, in an applied electric field of ${\pm}0.75\;MV/cm$.

• Korean Journal of Materials Research
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• v.15 no.4
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• pp.275-280
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• 2005

The growth of hafnium oxide thin films by atomic layer deposition was investigated in the temperature range of $175-350^{\circ}C$ using $Hf[N(CH_3)_2]_4\;and\;O_2$ as precursors. A self-limiting growth of $0.6\AA/cycle$ was achieved at the substrate temperature of $240-280^{\circ}C$. The films were amorphous and very smooth (0.76-0.80 nm) as examined by X-ray diffractometer and atomic force microscopy, respectively. X-ray photoelectron spectroscopy analysis showed that the films grown at $300^{\circ}C$ was almost stoichiometric. Electrical measurements performed on $MoW/HfO_2$(20 nm)/Si MOS structures exhibited high dielectric constant$(\~17)$ and a remarkably low leakage current density of at an applied field of $1.5-6.2\times10^{-7}A/cm^2$ MV/cm, probably due to the stoichiometry of the films.

• 한국태양에너지학회:학술대회논문집
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• 2011.11a
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• pp.245-248
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• 2011

Many researches have been carried out to improve light absorption in the crystalline silicon solar cell fabrication. The rear reflection is applied to increase the path length of light, resulting in the light absorption enhancement and thus the efficiency improvement mainly due to increase in short circuit current. In this paper, we manufactured the silicon solar cell using the mono crystalline silicon wafers with $156{\times}156mm^2$, 0.5~3.0 ${\Omega}{\cdot}cm$ of resistivity and p-type. After saw damage removal, the dielectric film ($SiN_x$)on the back surface was deposited, followed by surface texturing in the KOH solution. It resulted in single-side texturing wafer. Then the dielectric film was removed in the HF solution. The silicon wafers were doped with phosphorus by $POCl_3$ with the sheet resistance 50 ${\Omega}/{\Box}$ and then the silicon nitride was deposited on the front surface by the PECVD with 80nm thickness. The electrodes were formed by screen-printing with Ag and Al paste for front and back surface, respectively. The reflectance and transmittance for the single-sided and double-sided textured wafers were compared. The double-sided textured wafer showed higher reflectance and lower transmittance at the long wavelength region, compared to single-sided. The completed crystalline silicon solar cells with different back surface texture showed the conversion efficiency of 17.4% for the single sided and 17.3% for the double sided. The efficiency improvement with single-sided textured solar cell resulted from reflectance increase on back surface and light absorption enhancement.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.11-11
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• 2010

Thin-film-transistors (TFTs) that can be deposited at low temperature have recently attracted lots of applications such as sensors, solar cell and displays, because of the great flexible electronics and transparent. Transparent and flexible transistors are being required that high mobility and large-area uniformity at low temperature [1]. But, unfortunately most of TFT structures are used to be $SiO_2$ as gate dielectric layer. The $SiO_2$ has disadvantaged that it is required to high driving voltage to achieve the same operating efficiency compared with other high-k materials and its thickness is thicker than high-k materials [2]. To solve this problem, we find lots of high-k materials as $HfO_2$, $ZrO_2$, $SiN_x$, $TiO_2$, $Al_2O_3$. Among the High-k materials, $Al_2O_3$ is one of the outstanding materials due to its properties are high dielectric constant ( ~9 ), relatively low leakage current, wide bandgap ( 8.7 eV ) and good device stability. For the realization of flexible displays, all processes should be performed at very low temperatures, but low temperature $Al_2O_3$ grown by sputtering showed deteriorated electrical performance. Further decrease in growth temperature induces a high density of charge traps in the gate oxide/channel. This study investigated the effect of growth temperatures of ALD grown $Al_2O_3$ layers on the TFT device performance. The ALD deposition showed high conformal and defect-free dielectric layers at low temperature compared with other deposition equipments [2]. After ITO was wet-chemically etched with HCl : $HNO_3$ = 3:1, $Al_2O_3$ layer was deposited by ALD at various growth temperatures or lift-off process. Amorphous InGaZnO channel layers were deposited by rf magnetron sputtering at a working pressure of 3 mTorr and $O_2$/Ar (1/29 sccm). The electrodes were formed with electron-beam evaporated Ti (30 nm) and Au (70 nm) bilayer. The TFT devices were heat-treated in a furnace at $300^{\circ}C$ and nitrogen atmosphere for 1 hour by rapid thermal treatment. The electrical properties of the oxide TFTs were measured using semiconductor parameter analyzer (4145B), and LCR meter.

• Applied Chemistry for Engineering
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• v.25 no.5
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• pp.455-462
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• 2014

This work investigated the hydrophobic coating of silicate yellow phosphor powder in the form of divalent europium-activated strontium orthosilicate ($Sr_2SiO_4:Eu^{2+}$) by using an atmospheric pressure dielectric barrier discharge (DBD) plasma with argon as a carrier and hexamethyldisiloxane (HMDSO), toluene and n-hexane as precursors. After the plasma treatment of the phosphor powder, the lattice structure of orthosilicate was not altered, as confirmed by an X-ray diffractometer. The coated phosphor powder was characterized by scanning electron microscopy, fluorescence spectrophotometry and contact angle analysis (CAA). The CAA of the phosphor powder coated with the HMDSO precursor revealed that the water contact angle increased from $21.3^{\circ}$ to $139.5^{\circ}$ (max. $148.7^{\circ}$) and the glycerol contact angle from $55^{\circ}$ to $143.5^{\circ}$ (max. $145.3^{\circ}$) as a result of the hydrophobic coating, which indicated that hydrophobic layers were successfully formed on the phosphor powder surfaces. Further surface characterizations were performed by Fourier transform infrared spectroscopy and X-ray photoelectron spectrometry, which also evidenced the formation of hydrophobic coating layers. The phosphor coated with HMDSO exhibited a photoluminescence (PL) enhancement, but the use of toluene or n-hexane somewhat decreased the PL intensity. The results of this work suggest that the DBD plasma may be a viable method for the preparation of hydrophobic coating layer on phosphor powder.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.67-67
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• 2009

Due to the scaling down of the dielectrics thickness, the leakage currents arising from electron tunneling through the dielectrics has become the major technical barrier. Thus, much works has focused on the development of high k dielectrics in both cases of memories and CMOS fields. Among the high-k materials, $Al_2O_3$ considered as good candidate has been attracting much attentions, which own some good properties as high dielectric constant k value (~9), a high bandgap (~2eV) and elevated crystallization temperature, etc. Due to the easy control of ion energy and flux, low ownership and simple structure of the inductively coupled plasma (ICP), we chose it for high-density plasma in our study. And the $BCl_3$ was included in the gas due to the effective extraction of oxygen in the form of BClxOy compound. In this study, the etch characteristic of ALD deposited $Al_2O_3$ thin film was investigated in $BCl_3/N_2$ plasma. The experiment were performed by comparing etch rates and selectivity of $Al_2O_3$ over $SiO_2$ as functions of the input plasma parameters such as gas mixing ratio, DC-bias voltage and RF power and process pressure. The maximum etch rate was obtained under 15 mTorr process perssure, 700 W RF power, $BCl_3$(6 sccm)/$N_2$(14 sccm) plasma, and the highest etch selectivity was 1.9. We used the x-ray photoelectron spectroscopy (XPS) to investigate the chemical reactions on the etched surface. The Auger electron spectroscopy (AES) was used for elemental analysis of etched surface.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.477-477
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• 2008

For more than three decades, the gate dielectrics in CMOS devices are $SiO_2$ because of its blocking properties of current in insulated gate FET channels. As the dimensions of feature size have been scaled down (width and the thickness is reduced down to 50 urn and 2 urn or less), gate leakage current is increased and reliability of $SiO_2$ is reduced. Many metal oxides such as $TiO_2$, $Ta_2O_4$, $SrTiO_3$, $Al_2O_3$, $HfO_2$ and $ZrO_2$ have been challenged for memory devices. These materials posses relatively high dielectric constant, but $HfO_2$ and $Al_2O_3$ did not provide sufficient advantages over $SiO_2$ or $Si_3N_4$ because of reaction with Si substrate. Recently, $HfO_2$ have been attracted attention because Hf forms the most stable oxide with the highest heat of formation. In addition, Hf can reduce the native oxide layer by creating $HfO_2$. However, new gate oxide candidates must satisfy a standard CMOS process. In order to fabricate high density memories with small feature size, the plasma etch process should be developed by well understanding and optimizing plasma behaviors. Therefore, it is necessary that the etch behavior of $HfO_2$ and plasma parameters are systematically investigated as functions of process parameters including gas mixing ratio, rf power, pressure and temperature to determine the mechanism of plasma induced damage. However, there is few studies on the the etch mechanism and the surface reactions in $BCl_3$ based plasma to etch $HfO_2$ thin films. In this work, the samples of $HfO_2$ were prepared on Si wafer with using atomic layer deposition. In our previous work, the maximum etch rate of $BCl_3$/Ar were obtained 20% $BCl_3$/ 80% Ar. Over 20% $BCl_3$ addition, the etch rate of $HfO_2$ decreased. The etching rate of $HfO_2$ and selectivity of $HfO_2$ to Si were investigated with using in inductively coupled plasma etching system (ICP) and $BCl_3/Cl_2$/Ar plasma. The change of volume densities of radical and atoms were monitored with using optical emission spectroscopy analysis (OES). The variations of components of etched surfaces for $HfO_2$ was investigated with using x-ray photo electron spectroscopy (XPS). In order to investigate the accumulation of etch by products during etch process, the exposed surface of $HfO_2$ in $BCl_3/Cl_2$/Ar plasma was compared with surface of as-doped $HfO_2$ and all the surfaces of samples were examined with field emission scanning electron microscopy and atomic force microscope (AFM).

• Journal of the Korean institute of surface engineering
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• v.29 no.6
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• pp.809-815
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• 1996

$Y_2O_3$-based metal-insulator-semiconductor (MIS) structure on p-Si(100) has been studied. Films were prepared by UHV reactive ionized cluster beam deposition (r-ICBD) system. The base pressure of the system was about $1 \times 10^{-9}$ -9/ Torr and the process pressure $2 \times 10^{-5}$ Torr in oxygen ambience. Glancing X-ray diffraction(GXRD) and in-situ reflection high energy electron diffracton(RHEED) analyses were performed to investigate the crystallinity of the films. The results show phase change from amorphous state to crystalline one with increasingqr acceleration voltage and substrate temperature. It is also found that the phase transformation from $Y_2O_3$(111)//Si(100) to $Y_2O_3$(110)//Si(100) in growing directions takes place between $500^{\circ}C$ and $700^{\circ}C$. Especially as acceleration voltage is increased, preferentially oriented crystallinity was increased. Finally under the condition of above substrate temperature $700^{\circ}C$ and acceleration voltage 5kV, the $Y_2O_3$films are found to be grown epitaxially in direction of $Y_2O_3$(1l0)//Si(100) by observation of transmission electron microscope(TEM). Capacitance-voltage and current-voltage measurements were conducted to characterize Al/$Y_2O_3$/Si MIS structure with varying acceleration voltage and substrate temperature. Deposited $Y_2O_3$ films of thickness of nearly 300$\AA$ show that the breakdown field increases to 7~8MV /cm at the same conditon of epitaxial growing. These results also coincide with XPS spectra which indicate better stoichiometric characteristic in the condition of better crystalline one. After oxidation the breakdown field increases to 13MV /cm because the MIS structure contains interface silicon oxide of about 30$\AA$. In this case the dielectric constant of only $Y_2O_3$ layer is found to be $\in$15.6. These results have demonstrated the potential of using yttrium oxide for future VLSI/ULSI gate insulator applications.