• ETRI Journal
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• v.13 no.4
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• pp.10-24
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• 1991

본 연구에서는 기상 성장법 (VPE : vapor phase epitaxy) 으로 성장된 $n^+(Si:2X10^18cm^-3)$/$n(Si:1x10^17cm^-3)$구조의 시편 위에 SiN 과 감광막 등 식각 선택비가 서로 다른 두 물질로 보호된 소스와 드레인 사이의 게이트 형성 영역을 건식식각과 습식식각방법으로 리세스 에칭을 하여 형성한 후, 게이트를 자기정렬하여 형성시킬 수 있는 이중 리세스공정 기술을 개발하였고, 이를 통하여 전력용 MESFET 소자를 제작하였다.게이트 형성부분의 wide recess 폭은 건식식각으로 SiN을 측면식각(lateral etch) 함으로써 조절하였는데, 이 방법을 사용하여 MESFET 소자의 임계전압을 조절할 수 있고, 동시에 소스-드레인 항복전압을 30V 까지 향상시킬 수 있었다. 소스-드레인 항복전압은 wide recess 폭이 증가함에 따라, 그리고 게이트 길이가 길어짐에 따라 증가하는 경향을 보여주었다. 이 방법으로 제작한 여러종류의 MESFET 중에서 게이트 길이가 $2\mum$이고 소스-게이트 간격이 $3 \mum$인 MESFET의 전기적 특성은 최대 트랜스컨덕턴스가 120 mS/mm, 게이트 전압이 0.8V 일 때 포화드레인전류가 170~190mA/mm로 나타났다. 제작된 MESFET이 ($NH_4$)$_2$$S_x$ 용액에 담금처리될때 , 공기중에 노출된 게이트-드레인 사이의 n-GaAs층의 표면이 유황으로 보호되어 공기노출에 의한 표면 재산화막의 형성이 억제되었기 때문으로 사료된다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.93-94
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• 2007

다양한 LDD(lightly doped drain)에 따른 n-channel poly-Si TFT (thin film transistor)에 대하여 보고한다. 유리 기판 위에 ELA를 이용하여 만들어진 Polycrystalline silicon (poly-Si)은 TFT-LCD의 응용을 위한 재료로써 우수한 특성을 갖는다. 제작된 n-channel TFT는 절연층으로 $SiN_x$, $SiO_2$의 이중 구조를 갖는다. 다양한 LDD에 따른 n-channel poly-Si TFT의 문턱전압($V_{TH}$), ON/OFF 전류비 ($I_{ON}/I_{OFF}$), 포화전류($I_{DSAT}$)는 TFT의 보다 좋은 성능을 위해 연구된다. 짧은 LLD 길이를 가진 n-channel poly-Si TFT의 문턱전압은 작고, 포화전류의 값은 크다. 또한 긴 LLD 길이를 가진 n-channel poly-Si TFT는 작은 kink effect를 가진다.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.3
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• pp.67-71
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• 2014

An attempt to grow high quality GaN on silicon substrate using metal organic chemical vapor deposition (MOCVD), herein GaN epitaxial layers were grown on various Si(111) substrates. Thin Platinum layer was deposited on Si(111) substrate using sputtering, followed by thermal annealing to form Pt nano-clusters which act as masking layer during dry-etched with inductively coupled plasma-reactive ion etching to generate nano-patterned Si(111) substrate. In addition, micro-patterned Si(111) substrate with circle shape was also fabricated by using conventional photo-lithography technique. GaN epitaxial layers were subsequently grown on micro-, nano-patterned and conventional Si (111) substrate under identical growth conditions for comparison. The GaN layer grown on nano-patterned Si (111) substrate shows the lowest crack density with mirror-like surface morphology. The FWHM values of XRD rocking curve measured from symmetry (002) and asymmetry (102) planes are 576 arcsec and 828 arcsec, respectively. To corroborate an enhancement of the growth quality, the FWHM value achieved from the photoluminescence spectra also shows the lowest value (46.5 meV) as compare to other grown samples.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.626-626
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• 2013

P-N 접합에 의해 절연된 게이트를 통해 전류 통로를 제어하는 접합형 전계효과 트랜지스터(Junction Field Effect Transistors; JFETs)는, 입력 임피던스가 크고, 온도에 덜 민감하며, 제조가 간편하여 집적회로(IC) 제조가 용이하고, 동작의 해석이 단순하다는 장점을 가지고 있다. 특히 JFET는 선형적인 전류의 증폭 특성을 가지고 있으며, 잡음이작기 때문에, 감도가 우수한 음향 센서의 증폭회로, 선형성이 우수한 증폭회로, 입력 계측 증폭 회로 등에 주로 사용되고 있다. 기존에 사용되는 JFET 소자는 구조와 제조 공정에 따라서, 컷 오프 전압($V_{cut-off}$)과 드레인-소스 포화 전류($I_{DSS}$)의 변화가 심하게 발생하여, 소자의 전기적 특성 제어가 어렵고, 소자의 수율이 낮다는 문제점이 있다. 본 연구에서는 TCAD 시뮬레이션을 통해 게이트 전압에 의해 채널이 형성되는 채널 층의 상하부에 각각 $Si_xGe_{1-x}$로 이루어진 상부 및 하부 확산 저지층을 삽입한 JFET 소자 형성하여, 게이트 접합부의 접합 영역 확산을 저지하고, 상기 게이트 접합부가 계면에서 날카로운 농도 구배를 갖도록 함으로써, 공정 변화에 따른 전기적 특성의 편차가 작아지는 JFET 소자 구조를 만들어 전기적 특성을 개선하였다. JFET은 채널층에 삽입된 $Si_xGe_{1-x}$ 층의 두께, Ge 함유량 및 n채널층의 두께를 변화하였을 때, off 상태의 게이트-소스 전압이 감소한 반면에 드레인-소스 포화 전류($I_{DSS}$)와 컨덕턴스(gm) 값이 증가하였다. 삽입된 $Si_xGe_{1-x}$층이 Boron이 밖으로 확산되는 현상이 감소하여 채널이 좁아지는 현상을 막아 소자의 전기적 특성을 개선함으로써 제조공정의 변화에 관계없이 컷오프 전압을 정확하고 안정되게 제어할 수 있고 이를 통해 소자의 수율을 높일 수 있을 것으로 기대된다.

• Korean Journal of Materials Research
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• v.9 no.6
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• pp.599-603
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• 1999

We have investigated the growth characteristics of thick GaN on Sim substrate with AlN and low temperature GaN buffer layer. The vertical hydride vapor phase epitaxy system with $GaCl_3$ precursor was used for growth of GaN. AlN and GaN buffer layer were deposited on Si substrate to reduce the lattice mismatch and the thermal expansion coefficient mismatch between si and GaN. Optimization of deposition condition for AlN and low temperature GaN buffer layers were carried out. We studied the effects of growth temperature, V/III ratio on the properties of thick GaN. Surface morphology, growth rate and crystallinity of thick GaN were measured using Atomic Force Microscopy (AFM), $\alpha-step$-, Scanning Electron Microscopy (SEM) and X-Ray Diffractometer(XRD).

• Journal of the Korean Ceramic Society
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• v.37 no.1
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• pp.50-56
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• 2000

Precursor gels with the composition of xZrO2·(100-x)SiO2 systems (x=10, 20 and 30 mol%) were prepared by the sol-gel method. Kinetic parameters, such as activation energy, Avrami's exponent, n, and dimensionality crystal growth value, m, have been simultaneously calculated from the DTA data using Kissinger and Matusita equations. The crystallite size dependence of tetragonal to monoclinic transformation of ZrO2 was investigated using XRD, in relation to the fracture toughness. The crystallization of tetragonal ZrO2 occurred through 3-dimensional diffusiion controlled growth(n=m=2) and the activation energy for crystallization was calculated using Kissinger and Matusita equations, as about 310∼325±10kJ/mol. The growth of t-ZrO2, in proportion to the cube of radius, increased with increasing heating temperature and hteat-treatment time. It was suggested that the diffusion of Zr4+ ions by Ostwald ripening was rate-limiting process for thegrowth of t-ZrO2 crystallite size. The fracture toughness of xZrO2·(100-x)SiO2 systems glass ceramics increased with increasing crystallite size of t-ZrO2. The fracture toughness of 30ZrO2·70SiO2 system glass ceramics heated at 1,100℃ for 5h was 4.84 MPam1/2 at a critical crystaliite size of 40 nm.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11a
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• pp.197-200
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• 2001

In this letter, we report on the investigation of Ni/Si/Ni Ohmic contacts to n-type 4H-SiC. Ohmic contacts have been formed by a vacuum annealing and N$_2$ gas ambient annealing method at 950$^{\circ}C$ for 10 min. The specific contact resistivity($\rho$$\sub$c/), sheet resistance(R$\sub$S/), contact resistance(R$\sub$S/), transfer length(LT) were calculated from resistance(R$\sub$T/) versus contact spacing(d) measurements obtained from 10 TLM(transmission line method) structures. The resulting average values of vacuum annealing sample were $\rho$$\sub$c/=3.8x10$\^$-5/ Ω$\textrm{cm}^2$ , R$\sub$c/=4.9Ω, R$\sub$T/=9.8Ω and L$\sub$T/=15.5$\mu\textrm{m}$, resulting average values of another sample were $\rho$$\sub$c/=2.29x10$\^$-4/ Ω$\textrm{cm}^2$ , R$\sub$c/=12.9Ω, R$\sub$T/=25.8Ω. The Physical properties of contacts were examined using X-Ray Diffraction and Auger analysis, there was a uniform intermixing of the Si and Ni, migration of Ni into the SiC.

• Journal of the Korean Ceramic Society
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• v.24 no.1
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• pp.23-32
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• 1987

Synthesis of high purity ultrafine Si3N4 and ${\beta}$-Sialon powders was investigated via the simultaneous reduction and nitriding of amorphous SiO2, SiO2-Al2O3 system prepaerd by hydrolysis of alkoxides, using carbonablack as a reducing agent. In Si(OC2H5)4-C2H5 OH-H2 O-NH4OH system, hydrolysis rate increased with increasing reaction temperature and pH. Pure ${\alpha}$-Si3N4 was formed at 1350$^{\circ}C$ for 5 hrs in N2 atmosphere. In Si(OC2H5)4-Al(OC3H7)3-C6H6-H2 O-NH4OH system, weight loss increased as Si/Al ratio decreased. Single phase ${\beta}$-Sialon consisted of Si/Al=2 was formed at 1350$^{\circ}C$ in N2 and minor phases of ${\alpha}$-Si3N4, AIN, and X-phase were existed besides theSialon phase at other Si/Al ratios. The Si3N4 and Sialon powders synthesized from alkoxides consisted of uniform find particles of 0.05-0.2$\mu\textrm{m}$ in diameter, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.3
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• pp.180-184
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• 2002

In this paper, the electrical properties of PVD Ta and $TaN_x$ gate electrodes on $SiO_2$ and their thermal stabilities are investigated. The results show that the work functions of $TaN_x$ gate electrode are modified by the amount of N, which is controlled by the flow rate of $N_2$during reactive sputtering process. The thermal stability of Ta and $TaN_x$ with RTO-grown $SiO_2$ gate dielectrics is examined by changes in equivalent oxide thickness (EOT), flat-band voltage ($V_{FB}$), and leakage current after post-metallization anneal at high temperature in $N_2$ambient. For a Ta gate electrode, the observed decrease in EOT and leakage current is due to the formation of a Ta-incorporated high-K layer during the high temperature annealing. Less change in EOT and leakage current is observed for $TaN_x$ gate electrode. It is also shown that the frequency dispersion and hysteresis of high frequency CV curves are improved significantly by a post-metallization anneal.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.45 no.2
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• pp.242-248
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• 1996

The properties of TiN/TiSi$_{2}$ bilayer formed by a rapid thermal annealing is investigated when thin SiO$_{2}$ film exists at the Ti-Si interface. The competitive reaction for the TiN/TiSi_2 bilayer occurs above 600 .deg. C. The thickness of the TiSi$_{2}$ layer decreases with increasing SiO$_{2}$ film thickness and also decreases with increasing anneal temperture When the competitive reaction for the TiN/TiSi$_{2}$ bilayer is occured by rapid thermal annealing, the composition of TiN layer represents TiN$_{x}$O$_{y}$ due to the SiO$_{2}$ layer at the Ti-Si interface but the structures of the TiN and TiSi$_{2}$ layers were not changed.d.d.