• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.68-68
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• 2011

As feature size is smaller, new technology are needed in semiconductor factory such as gap-fill technology for sub 100nm, development of ALD equipment for Cu barrier/seed, oxide trench etcher technology for 25 nm and beyond, development of high throughput Cu CMP equipment for 30nm and development of poly etcher for 25 nm and so on. We are focus on gap-fill technology for sub-30nm. There are many problems, which are leaning, over-hang, void, micro-pore, delaminate, thickness limitation, squeeze-in, squeeze-out and thinning phenomenon in sub-30 nm gap fill. New gap-fill processes, which are viscous oxide-SOD (spin on dielectric), O3-TEOS, NF3 Based HDP and Flowable oxide have been attempting to overcome these problems. Some groups investigated SOD process. Because gap-fill performance of SOD is best and process parameter is simple. Nevertheless these advantages, SOD processes have some problems. First, material cost is high. Second, density of SOD is too low. Therefore annealing and curing process certainly necessary to get hard density film. On the other hand, film density by Flowable oxide process is higher than film density by SOD process. Therefore, we are focus on Flowable oxide. In this work, dielectric film were deposited by PECVD with TSA(Trisilylamine - N(SiH3)3) and NH3. To get flow-ability, the effect of plasma treatment was investigated as function of O2 plasma power. QMS (quadruple mass spectrometry) and FTIR was used to analysis mechanism. Gap-filling performance and flow ability was confirmed by various patterns.

• Advances in nano research
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• v.5 no.3
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• pp.261-279
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• 2017

Spectroscopic investigation of Si quantum dots (Si-QDs) embedded in silicon nitride was performed over a broad stoichiometry range to optimize light emission. Plasma-enhanced chemical vapor deposition was used to grow the $SiN_x$ films on Si (001) substrates. The film composition was controlled via the flow ratio of silane ($SiH_4$) and ammonia ($NH_3$) in the range of R = 0.45-1.0 allowed to vary the Si excess in the range of 21-62 at.%. The films were submitted to annealing at $1100^{\circ}C$ for 30 min in nitrogen to form the Si-QDs. The properties of as-deposited and annealed films were investigated using spectroscopic ellipsometry, Fourier transform infrared spectroscopy, Raman scattering and photoluminescence (PL) methods. Si-QDs were detected in $SiN_x$ films demonstrating the increase of sizes with Si excess. The residual amorphous Si clusters were found to be present in the films grown with Si excess higher than 50 at.%. Multi-component PL spectra at 300 K in the range of 1.5-3.5 eV were detected and nonmonotonous varying total PL peak versus Si excess was revealed. To identify the different PL components, the temperature dependence of PL spectra was investigated in the range of 20-300 K. The analysis allowed concluding that the "blue-orange" emission is due to the radiative defects in a $SiN_x$ matrix, whereas the "red" and "infrared" PL bands are caused by the exciton recombination in crystalline Si-QDs and amorphous Si clusters. The nature of radiative and no radiative defects in $SiN_x$ films is discussed. The ways to control the dominant PL emission mechanisms are proposed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.4
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• pp.202-208
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• 2001

In Recent results suggested that doping $Ta_2O_5$ with a small amount of $TiO_2$ using standard ceramic processing techniques can increase the dielectric constant of $Ta_2O_5$ significantly. In this paper, this concept is studied using RTCVD (Rapid Thermal Chemical Vapor Deposition). Ti-doped $Ta_2O_5$ films are deposited using $TaC_{12}H_{30}O_5N$, $C_8H_{24}N_4Ti$, and $O_2$ on both Si and $NH_3$-nitrided Si substrates. An $NH_3$-based interface layer at the Si surface is used to prevent interfacial oxidation during the CVD process and post deposition annealing is performed in $H_2/O_2$ ambient to improve film quality and reduce leakage current. A sputtered TiN layer is used as a diffusion barrier between the Al gate electrode and the $TaTi_xO_y$ dielectric. XPS analyses confirm the formation of a ($Ta_2O_5)_{1-x}(TiO_2)_x$ composite oxide. A high quality $TaTi_xO_y$ gate stack with EOT (Equivalent Oxide Thickness) of $7{\AA}$ and leakage current $Jg=O.5A/textrm{cm}^2$ @ Vg=-1.0V has been achieved. We have also succeeded in forming a $TaTi_x/O_y$ composite oxide by rapid thermal oxidation of the as-deposited CVD TaTi films. The electrical properties and Jg-EOT characteristics of these composite oxides are remarkably similar to that of RTCVD $Ta_2O_5, suggesting that the dielectric constant of $Ta_2O_5$ is not affected by the addition of $TiO_2$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.8
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• pp.655-659
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• 2010

Nanoporous titanium dioxide ($TiO_2$) is very attractive material for various applications due to the high surface to volume ratio. In this study, we have fabricated nanoporous $TiO_2$ thin films on Si by anodic oxidation. 500-nm-thick titanium (Ti) films were deposited on Si by using electron beam evaporation. Nanoporous structures in the Ti films were obtained by anodic oxidization using ethylene glycol electrolytes containing 0.3 wt% $NH_4F$ and 2 vol% $H_2O$ under an applied bias of 5 V. The diameter of nanopores in the Ti films linearly increased with anodization time and the whole Ti layer could become nanoporous after anodizing for 3 hours, resulting in vertically aligned nanotubes with the length of 200~300 nm and the diameter of 50~80 nm. Upon annealing at $600^{\circ}C$ in air, the anodized Ti films were fully crystallized to $TiO_2$ of rutile and anatase phases. We believe that our method to fabricate nanoporous $TiO_2$ films on Si is promising for applications to thin-film gas sensors and thin-film photovoltaics.

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.05a
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• pp.22.2-22.2
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• 2009

Currently, metal silicides become increasingly more essential part as a contact material in complimentary metal-oxide-semiconductor (CMOS). Among various silicides, NiSi has several advantages such as low resistivity against narrow line width and low Si consumption. Generally, metal silicides are formed through physical vapor deposition (PVD) of metal film, followed by annealing. Nanoscale devices require formation of contact in the inside of deep contact holes, especially for memory device. However, PVD may suffer from poor conformality in deep contact holes. Therefore, Atomic layer deposition (ALD) can be a promising method since it can produce thin films with excellent conformality and atomic scale thickness controllability through the self-saturated surface reaction. In this study, Ni thin films were deposited by thermal ALD using bis(dimethylamino-2-methyl-2-butoxo)nickel [Ni(dmamb)2] as a precursor and NH3 gas as a reactant. The Ni ALD produced pure metallic Ni films with low resistivity of 25 $\mu{\Omega}cm$. In addition, it showed the excellent conformality in nanoscale contact holes as well as on Si nanowires. Meanwhile, the Ni ALD was applied to area-selective ALD using octadecyltrichlorosilane (OTS) self-assembled monolayer as a blocking layer. Due to the differences of the nucleation on OTS modified surfaces toward ALD reaction, ALD Ni films were selectively deposited on un-coated OTS region, producing 3 ${\mu}m$-width Ni line patterns without expensive patterning process.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2005.05a
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• pp.139-145
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• 2005

In the study, in order to deposit TaN thin film using diffusion barrier and bottom electrode we made the Plasma Assisted ALD equipment and confirmed the electrical characteristic of TaN thin films deposited PAALD method, PAALD equipment depositing TaN thin film using PEMAT(pentakis(ethylmethlyamlno) tantalum) Precursor and $NH_3$ reaction gas is aware that TaN thin film deposited of high density and amorphous phase with XRD measurement The degree of diffusion and react ion taking place in Cu/TaN(deposited using 150 W PAALD)/$SiO_2$/Si systems with increasing annealing temperature was estimated from MOS capacitor property and the $SiO_2(600\;\AA)$/Si system surface analysis by C-V measurement and secondary ion material spectrometer(SIMS) after Cu/TaN/$SiO_2(400\;\AA)$ system etching. TaN thin film deposited PAALD method diffusion barrier have a good diffusion barrier property up to $500^{\circ}C$.

• Journal of the Semiconductor & Display Technology
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• v.4 no.2 s.11
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• pp.39-43
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• 2005

In the study, in order to deposit TaN thin film for diffusion barrier and bottom electrode we made the Plasma Assisted ALD equipment and confirmed the electrical characteristics of TaN thin films grown PAALD method. Plasma Assisted ALD equipment depositing TaN thin film using PEMAT(pentakis(ethylmethlyamino) tantalum) precursor and NH3 reaction gas is shown that TaN thin film deposited high density and amorphous phase with XRD measurement. The degree of diffusion and reaction taking place in Cu/TaN (deposited using 150W PAALD)/$SiO_{2}$/Si systems with increasing annealing temperature was estimated for MOS capacitor property and the $SiO_{2}$, (600${\AA}$)/Si system surface analysis by C-V measurement and secondary ion material spectrometer (SIMS) after Cu/TaN/$SiO_{2}$ (400 ${\AA}$) layer etching. TaN thin film deposited PAALD method diffusion barrier have a good diffusion barrier property up to 500$^{\circ}C$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.239-240
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• 2008

As semiconductor devices are scaled down for better performance and more functionality, the Cu-based interconnects suffer from the increase of the resistivity of the Cu wires. The resistivity increase, which is attributed to the electron scattering from grain boundaries and interfaces, needs to be addressed in order to further scale down semiconductor devices [1]. The increase in the resistivity of the interconnect can be alleviated by increasing the grain size of electroplating (EP)-Cu or by modifying the Cu surface [1]. Another possible solution is to maximize the portion of the EP-Cu volume in the vias or damascene structures with the conformal diffusion barrier and seed layer by optimizing their deposition processes during Cu interconnect fabrication, which are currently ionized physical vapor deposition (IPVD)-based Ta/TaN bilayer and IPVD-Cu, respectively. The use of in-situ etching, during IPVD of the barrier or the seed layer, has been effective in enlarging the trench volume where the Cu is filled, resulting in improved reliability and performance of the Cu-based interconnect. However, the application of IPVD technology is expected to be limited eventually because of poor sidewall step coverage and the narrow top part of the damascene structures. Recently, Ru has been suggested as a diffusion barrier that is compatible with the direct plating of Cu [2-3]. A single-layer diffusion barrier for the direct plating of Cu is desirable to optimize the resistance of the Cu interconnects because it eliminates the Cu-seed layer. However, previous studies have shown that the Ru by itself is not a suitable diffusion barrier for Cu metallization [4-6]. Thus, the diffusion barrier performance of the Ru film should be improved in order for it to be successfully incorporated as a seed layer/barrier layer for the direct plating of Cu. The improvement of its barrier performance, by modifying the Ru microstructure from columnar to amorphous (by incorporating the N into Ru during PVD), has been previously reported [7]. Another approach for improving the barrier performance of the Ru film is to use Ru as a just seed layer and combine it with superior materials to function as a diffusion barrier against the Cu. A RulTaN bilayer prepared by PVD has recently been suggested as a seed layer/diffusion barrier for Cu. This bilayer was stable between the Cu and Si after annealing at $700^{\circ}C$ for I min [8]. Although these reports dealt with the possible applications of Ru for Cu metallization, cases where the Ru film was prepared by atomic layer deposition (ALD) have not been identified. These are important because of ALD's excellent conformality. In this study, a bilayer diffusion barrier of Ru/TaCN prepared by ALD was investigated. As the addition of the third element into the transition metal nitride disrupts the crystal lattice and leads to the formation of a stable ternary amorphous material, as indicated by Nicolet [9], ALD-TaCN is expected to improve the diffusion barrier performance of the ALD-Ru against Cu. Ru was deposited by a sequential supply of bis(ethylcyclopentadienyl)ruthenium [Ru$(EtCp)_2$] and $NH_3$plasma and TaCN by a sequential supply of $(NEt_2)_3Ta=Nbu^t$ (tert-butylimido-trisdiethylamido-tantalum, TBTDET) and $H_2$ plasma. Sheet resistance measurements, X-ray diffractometry (XRD), and Auger electron spectroscopy (AES) analysis showed that the bilayer diffusion barriers of ALD-Ru (12 nm)/ALD-TaCN (2 nm) and ALD-Ru (4nm)/ALD-TaCN (2 nm) prevented the Cu diffusion up to annealing temperatures of 600 and $550^{\circ}C$ for 30 min, respectively. This is found to be due to the excellent diffusion barrier performance of the ALD-TaCN film against the Cu, due to it having an amorphous structure. A 5-nm-thick ALD-TaCN film was even stable up to annealing at $650^{\circ}C$ between Cu and Si. Transmission electron microscopy (TEM) investigation combined with energy dispersive spectroscopy (EDS) analysis revealed that the ALD-Ru/ALD-TaCN diffusion barrier failed by the Cu diffusion through the bilayer into the Si substrate. This is due to the ALD-TaCN interlayer preventing the interfacial reaction between the Ru and Si.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.341-341
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• 2016

The discovery of light emission in nanostructured silicon has opened up new avenues of research in nano-silicon based devices. One such pathway is the application of silicon quantum dots in advanced photovoltaic and light emitting devices. Recently, there is increasing interest on the silicon quantum dots (c-Si QDs) films embedded in amorphous hydrogenated silicon-nitride dielectric matrix (a-SiNx: H), which are familiar as c-Si/a-SiNx:H QDs thin films. However, due to the limitation of the requirement of a very high deposition temperature along with post annealing and a low growth rate, extensive research are being undertaken to elevate these issues, for the point of view of applications, using plasma assisted deposition methods by using different plasma concepts. This work addresses about rapid growth and single step development of c-Si/a-SiNx:H QDs thin films deposited by RF (13.56 MHz) and ultra-high frequency (UHF ~ 320 MHz) low-pressure plasma processing of a mixture of silane (SiH4) and ammonia (NH3) gases diluted in hydrogen (H2) at a low growth temperature ($230^{\circ}C$). In the films the c-Si QDs of varying size, with an overall crystallinity of 60-80 %, are embedded in an a-SiNx: H matrix. The important result includes the formation of the tunable QD size of ~ 5-20 nm, having a thermodynamically favorable <220> crystallographic orientation, along with distinct signatures of the growth of ${\alpha}$-Si3N4 and ${\beta}$-Si3N4 components. Also, the roles of different plasma characteristics on the film properties are investigated using various plasma diagnostics and film analysis tools.

• Korean Journal of Materials Research
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• v.2 no.3
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• pp.180-190
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• 1992

Some solutions to several major problems in ZMR such as agglomeration of polysilicon, slips and local substrate melting are described. Experiments are performed with varying polysilicon thickness and capping oxide thickness. The aggmeration can be eliminated when nitrogen is introduced at the capping oxide layer-to-polysilicon interface and polysilicon-to-buried oxide layer interface by annealing the SOI samples at $1100^{\circ}$ in $NH_3$ ambient for three hours. The slips and local substrate melting are removed when the back surface of silicon substrate is sandblasted to produce the back surface roughness of about $20{\mu}m$. The subboundary spacing increases with increasing polysilicon thickness and the uniformity of recrystallized SOI film thickness improves with increasing capping oxide thickness, improving the quality of recrystallized SOI film. When the polysilicon thickness is about $1.0{\mu}m$ and the capping oxide thickness is $2.5{\mu}m$, the thickness variation of the recrystallized SOI film is about ${\pm}200{\AA}$ and the subboundary spacing is about $70-120{\mu}m$.