• Journal of the Korean Crystal Growth and Crystal Technology
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• v.13 no.2
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• pp.56-62
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• 2003

Epitaxial $Bi_4Ti_3O_{12}$ films on $SrTiO_3$(100), L$aA1O_3$(100) and MgO(100) were prepared by sol-gel process using metal naphthenate as a starting material. As-deposited films were pyrolyzed at $500^{\circ}C$ for 10 min In air and annealed at $750^{\circ}C$ for 30 min in air. Crystallinity and in-plane alignment of the film were investigated by X-ray diffraction $\theta$-2$\theta$ scan and P scanning. A field emission-scanning electron microscope and an atomic force microscope were used for characterizing the surface morphology and the surface roughness of the film. The film prepared on MgO(100) showed the most poor crystallinity and in-plane alignment, compared to those on the other substrates. While the films on $LaA1O_3$(100) and $SrTiO_3$(100) having high crystallinity and in-plane alignment showed the form of columnar grain growth, the film on MgO(100) which had poor crystallinity showed the form of acicula grain growth.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.7
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• pp.575-580
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• 2007

A 16 Mb 1T1C FeRAM device was integrated with BLT capacitors. But a lot of cells were failed randomly during the measuring the bit-line signal distribution of each cell. The reason was revealed that the grain size and orientation of the BLT thin film were severely non-uniform. And the grain size and orientation were severely affected by the process conditions of post heat treatment, especially nucleation step. The optimized annealing temperature at the nucleation step was $560^{\circ}C$. The microstructure of the BLT thin film was also varied by the annealing time at the step. The longer process time showed the finer grain size. Therefore, the uniformity of the grain size and orientation could be improved by changing the process conditions of the nucleation step. The FeRAM device without random bit-fail cell was successfully fabricated with the optimized BLT capacitor and the sensing margin in bit-line signal distribution of it was about 340 mV.

• Korean Journal of Materials Research
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• v.13 no.12
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• pp.846-849
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• 2003

Doping effect of various ions in Bi-layered ferroelectric $SrBi_2$$Nb_2$$O_{9}$ (SBN) ceramics was studied. Undoped SBN ceramic and SBN ceramics doped with $Ba^{2＋}$, $Pb^{2＋}$,$ Ca^{2＋}$ , $Bi^{3＋}$ , $La^{3＋}$ , $Ti^{4＋}$ , $Mo^{6＋}$ , and $W^{6＋}$ ions were made by a solid state reaction. Dielectric constants were measured with temperature. Ferroelectric transition temperature decreased with $Pb^{2＋}$ , $Ba^{2＋}$ , $La^{3＋}$ doping, but the transition temperature increased with $Ca^{2＋}$ , $Bi^{3＋}$ , $Ti^{4＋}$, $Mo^{6＋}$ , or$ W^{6＋}$ ionic doping. These results show that the ion size plays an important role in the ferroelectricity of SBN ceramic.

• Proceedings of the Korean Powder Metallurgy Institute Conference
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• 2006.09a
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• pp.533-534
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• 2006

1mm-thick BLT ceramics were sintered in accordance with a bulk ceramic fabrication process. All XRD peaks detected in the sintered ceramics were indexed as the Bi-layered perovskite structure without secondary phases. Density was increased with increasing the sintering temperature up to $1050\;^{\circ}C$ and the maximum value was about 98% of the theoretical density. The remanent polarization (2Pr) value of BLT ceramic sintered at $1050\;^{\circ}C$ was approximately $6.5\;{\mu}C/cm^2$ at the applied voltage of 4.5kV. From these results, a BLT ceramic target for plused laser deposition (PLD) system was successfully fabricated.

• Proceedings of the Korean Vacuum Society Conference
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• 2004.02a
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• pp.65-65
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• 2004

• 한국전자현미경학회:학술대회논문집
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• 2003.11a
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• pp.49-51
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• 2003

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.4
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• pp.265-271
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• 2003

Ferroelectric lanthanum-substituted Bi$_4$Ti$_3$O$_{12}$(BLT) thin films were fabricated by spin-coating onto a Pt/Ti/SiO$_2$/Si substrate by metalorganic decomposition technique. The grain size in BLT thin films were prepared with controlled by various drying process. The effect of grain size on the crystallization and ferroelectric properties were investigated by x-ray diffraction and field emission scanning electron microscope. The dependence of crystallization and electrical properties are related to the grain size in BLT thin films with different drying temperature. The remanent polarization of BLT thin film increases with the increasing grain size. The value of 2P$_{r}$ and E$_{c}$ of BLT thin film dried at 45$0^{\circ}C$ were 25.9 $\mu$C/$\textrm{cm}^2$ and 85 kV/cm, respectively. The BLT thin film with larger grain size has better fatigue properties. The fatigue properties revealed that small grained film showed more degradation of switching charge than large grained films.lms.s.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.3
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• pp.223-227
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• 2007

The effect of Eu contents on the ferroelectric properties of $Bi_{4-x}Eu_xTi_3 O_{12}$ (BET) thin films has been investigated. Bismuth Europium titanate thin films with a Eu contents were prepared on the $Pt/Ti/SiO_2/Si$ substrate by metal-organic decomposition technique. The structure and the morphology of the films were analyzed using X-ray diffraction (XRD) and field emission scanning microscopy (FE-SEM), respectively. From the XRD analysis, it was found that BET thin films have polycrystalline structure, and the layered-perovskite phase is obtained when the Eu contents exceeds 0.2 (x > 0.2). Also, the ferroelectric characteristics of the BET thin films were found to be dependent on the Eu content. Particularly, the BET films doped with x = 0.75 show better ferroelectric properties (remanent polarization 2Pr = 60.99 C/$cm^2$ and only a little polarization fatigue up to $3.5{\times}10^9$ bipolar switching cycling) than those doped with other Eu contents.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.1 s.34
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• pp.21-26
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• 2005

The field effect transistors (FETs) were fabricated ell $Y_2O_3/Si(100)$ substrates by the conventional memory processes and sol-gel process using $(Bi,La)Ti_3O_{12}(BLT)$ ferroelectric gate materials. The remnant polarization ($2Pr = Pr^+-Pr^-$) int Pt/BLT/Pt/Si capacitors increased from $22 {\mu}C/cm^2$ to $30{\mu}C/ cm^2$ at 5V as the annealing temperature increased from $700^{\circ}C$ to $750^{\circ}C$. There was no drastic degradation in the polarization values after applying the retention read pulse for $10^{5.5}$ seconds. The capacitance-voltage data of $Pt/BLT/Y_2O_3/Si$ capacitors at 5V input voltage showed that the memory window voltage decreased from 1.4V to 0.6V as the annealing temperature increased from $700^{\circ}C$ to $750^{\circ}C$. The leakage current of the $Pt/BLT/Y_2O_3/Si$ capacitors annealed at $750^{\circ}C$ was about $510^{-8}A/cm^2$ at 5V. From the drain currents versus gate voltages ($V_G$) for $Pt/BLT/Y_2O_3/Si(100)$ FET devices, the memory window voltages increased from 0.3V to 0.8V with increasing tile $V_G$ from 3V to 5V.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.221-225
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• 2003

The MFIS-FET(Field Effect Transistor) devices using $BLT/Y_2O_3$ buffer layer on p-Si(100) substrates were fabricated by the Sol-Gel method and conventional memory processes. The crystal structure, morphologies and electrical properties of prepared devices were investigated by using various measuring techniques. From the C-V(capacitance-voltage) data at 5V, the memory window voltage of the $Pt/BLT/Y_2O_3/si$ structure decreased from 1.4V to 0.6V with increasing the annealing temperature from $700^{\circ}C\;to\;750^{\circ}C$. The drain current (Ic) as a function of gate voltages $(V_G)$ for the $MFIS(Pt/BLT/Y_2O_3/Si(100))-FET$ devices at gate voltages $(V_G)$ of 3V, 4V and 5V, the memory window voltages increased from 0.3V to 0.8V as $V_G$ increased from 3V to 5V.