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http://dx.doi.org/10.5573/JSTS.2014.14.4.484

A PVT-compensated 2.2 to 3.0 GHz Digitally Controlled Oscillator for All-Digital PLL  

Kavala, Anil (Inter-University Semiconductor Research Center (ISRC) and the School of Electrical and Computer Engineering, Seoul National University)
Bae, Woorham (Inter-University Semiconductor Research Center (ISRC) and the School of Electrical and Computer Engineering, Seoul National University)
Kim, Sungwoo (Inter-University Semiconductor Research Center (ISRC) and the School of Electrical and Computer Engineering, Seoul National University)
Hong, Gi-Moon (Inter-University Semiconductor Research Center (ISRC) and the School of Electrical and Computer Engineering, Seoul National University)
Chi, Hankyu (Inter-University Semiconductor Research Center (ISRC) and the School of Electrical and Computer Engineering, Seoul National University)
Kim, Suhwan (Inter-University Semiconductor Research Center (ISRC) and the School of Electrical and Computer Engineering, Seoul National University)
Jeong, Deog-Kyoon (Inter-University Semiconductor Research Center (ISRC) and the School of Electrical and Computer Engineering, Seoul National University)
Publication Information
JSTS:Journal of Semiconductor Technology and Science / v.14, no.4, 2014 , pp. 484-494 More about this Journal
Abstract
We describe a digitally controlled oscillator (DCO) which compensates the frequency variations for process, voltage, and temperature (PVT) variations with an accuracy of ${\pm}2.6%$ at 2.5 GHz. The DCO includes an 8 phase current-controlled ring oscillator, a digitally controlled current source (DCCS), a process and temperature (PT)-counteracting voltage regulator, and a bias current generator. The DCO operates at a center frequency of 2.5 GHz with a wide tuning range of 2.2 GHz to 3.0 GHz. At 2.8 GHz, the DCO achieves a phase noise of -112 dBc/Hz at 10 MHz offset. When it is implemented in an all-digital phase-locked loop (ADPLL), the ADPLL exhibits an RMS jitter of 8.9 ps and a peak to peak jitter of 77.5 ps. The proposed DCO and ADPLL are fabricated in 65 nm CMOS technology with supply voltages of 2.5 V and 1.0 V, respectively.
Keywords
Digitally controlled oscillator; ring oscillator; PVT compensated DCO; PT-counteracting voltage regulator; all-digital phase-locked loop;
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1 D.-H. Oh, K.-J. Choo, and D.-K. Jeong, "Phase-frequency detecting time-to-digital converter," IET Electronics Letters, vol. 45, no: 4, pp.201-202, Dec. 2009.   DOI   ScienceOn
2 M. Nekili, Y. Savaria, and G. Bois, "Spatial characterization of process variations via MOS transistor time constants in VLSI and WSI," IEEE J. Solid-State Circuits, vol. 34, no. 1, pp. 80-84, Jan. 1999.   DOI   ScienceOn
3 I. M. Filanovsky and A. Allam, "Mutual compensation of mobility and threshold voltage temperature effects with applications in CMOS circuits," IEEE Trans. on Circuits Syst. I, Fundamental Theory and Applications, vol. 48, no. 7, pp. 876-884, July 2001.   DOI   ScienceOn
4 T. Olsson and P. Nilsson, "A digitally controlled PLL for SoC Applications," IEEE J. Solid-State Circuits, vol. 39, no. 5, pp. 451-460, May 2004.
5 D.-S. Kim, H. Song, T. Kim, S. Kim, and D.-K. Jeong , "A 0.3-1.4 GHz all-digital fractional-N PLL with adaptive loop gain controller," IEEE J. Solid-State Circuits, vol. 45, no. 11, pp. 2300-2311, Nov. 2010.
6 D.-H. Oh, D.-S. Kim, S. Kim, D.-K. Jeong, and W. Kim, "A 2.8Gb/s all-digital CDR with a 10b monotonic DCO," in Proc. IEEE Int. Solid-State Circuits Conf., pp.222-598, 2007.
7 H. Song, D.-S. Kim, D.-H. Oh, S. Kim, and D.-K. Jeong, "A 1.0-4.0-Gb/s all-digital CDR with 1.0-ps period resolution DCO and adaptive proportional gain control," IEEE J. Solid-State Circuits, vol. 46, no. 2, pp. 424-434, Feb. 2011.   DOI   ScienceOn
8 C.-F. Tsai, W.-J. Li, P.-Y. Chen, Y.-Z. Lin, and S.- J. Chang, "On-chip reference oscillators with process, supply voltage and temperature compensation," in Proc. Int. Symp. Next- Generation Electronics, pp. 108-111, 2010, Taiwan.
9 X. Zhang and A. B. Apsel, "A low-power, processand- temperature -compensated ring oscillator with addition-based current source," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 58, pp. 868-878, 2011.   DOI   ScienceOn
10 R. Vijayaraghavan, S. K. Islam, M. R. Haider, and L. Zuo, "Wideband injection-locked frequency divider based on a process and temperature compensated ring oscillator," IET Circuits, Devices & Syst., vol. 3, pp. 259-267, 2009.   DOI   ScienceOn
11 K. R. Lakshmikumar, V. Mukundagiri, and S. L. J. Gierkink, "A process and temperature compensated two-stage ring oscillator," in Proc. IEEE Custom Integr. Circuits Conf., pp. 691-694, 2007.
12 Y.-S. Park and W.-Y. Choi, "On-chip compensation of ring VCO oscillation frequency changes due to supply noise and process variation," IEEE Trans. Circuits Sys.-II, Exp. Briefs, vol. 59, no. 2, pp. 73-77, Feb. 2012.   DOI   ScienceOn