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| 1 |
The Effects of Nanocrystalline Silicon Thin Film Thickness on Top Gate Nanocrystalline Silicon Thin Film Transistor Fabricated at 180℃
Kang, Dong-Won;Park, Joong-Hyun;Han, Sang-Myeon;Han, Min-Koo;
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The Institute of Electronics and Information Engineers
, v.8, no.2, pp.111-114,
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| 2 |
Extraction of Effective Carrier Velocity and Observation of Velocity Overshoot in Sub-40 nm MOSFETs
Kim, Jun-Soo;Lee, Jae-Hong;Yun, Yeo-Nam;Park, Byung-Gook;Lee, Jong-Duk;Shin, Hyung-Cheol;
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The Institute of Electronics and Information Engineers
, v.8, no.2, pp.115-120,
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| 3 |
Design and Fabrication of Electrostatic Inkjet Head using Silicon Micromachining Technology
Kim, Young-Min;Son, Sang-Uk;Choi, Jae-Yong;Byun, Do-Young;Lee, Suk-Han;
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The Institute of Electronics and Information Engineers
, v.8, no.2, pp.121-127,
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| 4 |
Core Circuit Technologies for PN-Diode-Cell PRAM
Kang, Hee-Bok;Hong, Suk-Kyoung;Hong, Sung-Joo;Sung, Man-Young;Choi, Bok-Gil;Chung, Jin-Yong;
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The Institute of Electronics and Information Engineers
, v.8, no.2, pp.128-133,
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| 5 |
Power-Gating Structure with Virtual Power-Rail Monitoring Mechanism
Lee, Hyoung-Wook;Lee, Hyun-Joong;Woo, Jong-Kwan;Shin, Woo-Yeol;Kim, Su-Hwan;
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The Institute of Electronics and Information Engineers
, v.8, no.2, pp.134-138,
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| 6 |
X Band 7.5 W MMIC Power Amplifier for Radar Application
Lee, Kyung-Ai;Chun, Jong-Hoon;Hong, Song-Cheol;
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The Institute of Electronics and Information Engineers
, v.8, no.2, pp.139-142,
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| 7 |
Design of a 2.4-GHz Fully Differential Zero-IF CMOS Receiver Employing a Novel Hybrid Balun for Wireless Sensor Network
Chang, Shin-Il;Park, Ju-Bong;Won, Kwang-Ho;Shin, Hyun-Chol;
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The Institute of Electronics and Information Engineers
, v.8, no.2, pp.143-149,
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| 8 |
BER Simulator Development for Link Compliance Analysis
Kang, Hyun-Chul;Kim, Woo-Seop;Lee, Jae-Wook;Jang, Young-Chan;Park, Hwan-Wook;Kim, Jong-Hoon;Lee, Jung-Bae;Kim, Chang-Hyun;
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The Institute of Electronics and Information Engineers
, v.8, no.2, pp.150-155,
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| 9 |
Design Consideration of Bulk FinFETs with Locally-Separated-Channel Structures for Sub-50 nm DRAM Cell Transistors
Jung, Han-A-Reum;Park, Ki-Heung;Lee, Jong-Ho;
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The Institute of Electronics and Information Engineers
, v.8, no.2, pp.156-163,
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| 10 |
Study of the Effects of the Antisite Related Defects in Silicon Dioxide of Metal-Oxide-Semiconductor Structure on the Gate Leakage Current
Mao, Ling-Feng;Wang, Zi-Ou;Xu, Ming-Zhen;Tan, Chang-Hua;
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The Institute of Electronics and Information Engineers
, v.8, no.2, pp.164-169,
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| 11 |
Optimizing Effective Channel Length to Minimize Short Channel Effects in Sub-50 nm Single/Double Gate SOI MOSFETs
Sharma, Sudhansh;Kumar, Pawan;
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The Institute of Electronics and Information Engineers
, v.8, no.2, pp.170-177,
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