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1 Modeling and Optimization of $sub-0.1\;{\mu}m$ gate Metamorphic High Electron Mobility Transistors
Han Min;Kim Sam-Dong;Rhee Jin-Koo; / The Institute of Electronics and Information Engineers , v.42, no.3, pp.1-8,
2 Electron Mobility Model in Strained Si Inversion Layer
Park Il-Soo;Won Taeyoung; / The Institute of Electronics and Information Engineers , v.42, no.3, pp.9-16,
3 Optical packaging technology and characterization of analog PIN-Photodiode
Lee Chang Min;Kwon Kee Young; / The Institute of Electronics and Information Engineers , v.42, no.3, pp.17-24,
4 Characterization of Electrical Crosstalk in 1.25 Gbps Optoelectrical Triplex Transceiver Module for Ethernet Passive Optical Networks
Kim Sung-Il;Lee Hai-Young; / The Institute of Electronics and Information Engineers , v.42, no.3, pp.25-34,
5 A New Reseeding Methodology Using a Variable-Length Multiple-Polynomial LFSR
Yang Myung-Hoon;Kim Youbean;Lee Yong;Park Hyuntae;Kang Sungho; / The Institute of Electronics and Information Engineers , v.42, no.3, pp.35-42,
6 Design of Synchronous Quaternary Counter using Quaternary Logic Gate Based on Neuron-MOS
Choi Young-Hee;Yoon Byoung-Hee;Kim Heung-Soo; / The Institute of Electronics and Information Engineers , v.42, no.3, pp.43-50,