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| 1 |
Analysis of Effective Gate resistance characteristics in Nano-scale MOSFET for RFIC
윤형선;임수;안정호;이희덕;
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The Institute of Electronics and Information Engineers
, v.41, no.11, pp.1-6,
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| 2 |
Hydrogen-Related Gate Oxide Degradation Investigated by High-Pressure Deuterium Annealing
이재성;
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The Institute of Electronics and Information Engineers
, v.41, no.11, pp.7-13,
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| 3 |
Experimental Extraction of Effective Permittivity on the Structures of Coplanar Waveguides
지용;
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The Institute of Electronics and Information Engineers
, v.41, no.11, pp.15-20,
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| 4 |
Studies on the High-gain Low Noise Amplifier for 60 GHz Wireless Local Area Network
조창식;안단;이성대;백태종;진진만;최석규;김삼동;이진구;
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The Institute of Electronics and Information Engineers
, v.41, no.11, pp.21-27,
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| 5 |
RF Dispersion and Linearity Characteristics of AlGaN/InGaN/GaN HEMTs
Lee, Jong-Uk;
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The Institute of Electronics and Information Engineers
, v.41, no.11, pp.29-34,
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| 6 |
A Design of 250-MSamples/s 8-Bit Folding Analog to Digital Converter using Transistor Differential Pair Folding Technique
이돈섭;곽계달;
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The Institute of Electronics and Information Engineers
, v.41, no.11, pp.35-42,
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| 7 |
Fully Phase-based Optical Encryption System Using Computer Holography and Fresnel Diffraction
윤경효;신창목;조규보;김수중;김철수;서동환;
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The Institute of Electronics and Information Engineers
, v.41, no.11, pp.43-51,
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| 8 |
Efficient Capacitance Extraction Method for 3D Interconnect Models
김정학;성윤모;김석윤;
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The Institute of Electronics and Information Engineers
, v.41, no.11, pp.53-59,
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| 9 |
A Study on IEEE 1149.1 TAP Test Methodology for Minimum Area Overhead
김문준;장훈;
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The Institute of Electronics and Information Engineers
, v.41, no.11, pp.61-68,
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| 10 |
A Minimized Test Pattern Generation Method for Ground Bounce Effect and Delay Fault Detection
김문준;이정민;장훈;
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The Institute of Electronics and Information Engineers
, v.41, no.11, pp.69-77,
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| 11 |
Jitter Noise Suppression in the Digital DLL by a New Counter with Hysteretic Bit Transitions
정인영;손영수;
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The Institute of Electronics and Information Engineers
, v.41, no.11, pp.79-85,
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| 12 |
An Efficient Test Data Compression/Decompression Using Input Reduction
전성훈;임정빈;김근배;안진호;강성호;
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The Institute of Electronics and Information Engineers
, v.41, no.11, pp.87-95,
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| 13 |
Architecture Design of Line based Lifting-DWT for JPEG2000 Image Compression
정갑천;박성모;
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The Institute of Electronics and Information Engineers
, v.41, no.11, pp.97-104,
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| 14 |
A design of The Embedded 3n Graphics Rendering Processor for Portable Devices
우현재;장태홍;이문기;
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The Institute of Electronics and Information Engineers
, v.41, no.11, pp.105-113,
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| 15 |
An Implementation of Automatic Boundary Scan Circuit Generator Supporting Private Instructions
박재흥;장훈;
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The Institute of Electronics and Information Engineers
, v.41, no.11, pp.115-121,
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| 16 |
A Study on Multiplier Architectures Optimized for 32-bit RISC Processor with 3-Stage Pipeline
정근영;박주성;김석찬;
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The Institute of Electronics and Information Engineers
, v.41, no.11, pp.123-130,
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