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1 Analysis of Anomalous Subthreshold Characteristics in Ligtly-Doped Asymmetric Double-Gate MOSFETs
이혜림;신형순; / The Institute of Electronics and Information Engineers , v.40, no.6, pp.379-383,
2 The Algorithm for Calculating the Base-Collector Breakdown Voltage of NPN BJT Using the Solution of the Poisson′s Equation
이은구;김태한;김철성; / The Institute of Electronics and Information Engineers , v.40, no.6, pp.384-392,
3 Fabrication and Characteristics of 300V Mo-MPS Rectifier
최형호;박근용;김준식;최시영; / The Institute of Electronics and Information Engineers , v.40, no.6, pp.393-399,
4 Optical Security System Based on the Phase Characteristic of Joint Transform Correlator
박세준;서동환;김수종; / The Institute of Electronics and Information Engineers , v.40, no.6, pp.400-407,
5 A Wide - Range Dual-Loop DLL with Programmable Skew - Calibration Circuitry for Post Package
Choi, Sung-Il;Moon, Gyu;Wee, Jae-Kyung; / The Institute of Electronics and Information Engineers , v.40, no.6, pp.408-420,
6 Design of the Embedded EPROM Circuits Aiming at Low Voltage Operation
최상신;김성식;조경록; / The Institute of Electronics and Information Engineers , v.40, no.6, pp.421-430,
7 The Design of 32 Bit Microprocessor for Sequence Control Using FPGA
Yang, Oh; / The Institute of Electronics and Information Engineers , v.40, no.6, pp.431-441,
8 A Two-Stage Two-Phase Boosted Voltage Generator for Low-Voltage DRAMs
조성익;유성한;박무훈;김영희; / The Institute of Electronics and Information Engineers , v.40, no.6, pp.442-446,
9 A 32${\times}$32-b Multiplier Using a New Method to Reduce a Compression Level of Partial Products
홍상민;김병민;정인호;조태원; / The Institute of Electronics and Information Engineers , v.40, no.6, pp.447-458,
10 High-Speed Reed-Solomon Decoder Using New Degree Computationless Modified Euclid´s Algorithm
백재현;선우명훈; / The Institute of Electronics and Information Engineers , v.40, no.6, pp.459-468,