반도체디스플레이기술학회지 (Journal of the Semiconductor & Display Technology)

한국반도체디스플레이기술학회 (The Korean Society Of Semiconductor & Display Technology)
권호 표지

메모리 효율성을 높이기 위한 압축 명령어를 지원하는 32-비트 파이프라인 RISC-V프로세서 설계 및 구현

A Design and Implementation of 32-bit Pipeline RISC-V Processor Supporting Compressed Instructions for Memory Efficiency

  • 심현진 (상명대학교 시스템반도체공학과) ;
  • 김용우 (한국교원대학교 기술교육과)
  • Hyeonjin Sim (Department of System Semiconductor Engineering, Sangmyung University) ;
  • Yongwoo Kim (Department of Technology Education, Korea National University of Education)
  • 투고 : 2024.06.04
  • 심사 : 2024.09.12
  • 발행 : 2024.09.30
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초록

With the development of technologies such as the Internet of Things (IoT) and autonomous vehicles, research is being conducted on embedded processors that meet high performance, low power, and memory efficiency. The "C" expansion of the RISC-V processor is required to increase memory efficiency. In this paper, we propose an RV32IC processor and compare the benchmark performance score of the RV32I processor with the code size generated by the GCC compiler. In addition, we propose memory access and combination methods to support 16-bit compression commands, and command extension methods. The proposed RV32IC processor satisfies the maximum operating frequency of 50 MHz on the Artix-7 FPGA. The performance was checked using the benchmark programs of the Dhrystone and Coremark, and the code sizes of the RV32I and RV32IC generated by the GCC compiler were compared. The proposed processor RV32IC decreased DMIPS/MHz by 2.72% and Coremark/MHz by 0.61% compared to RV32I, but Coremark's code size decreased by 14.93%.

키워드

과제정보

이 논문은 한국교원대학교 2024학년도 신임교수 학술연구비 지원을 받아 수행한 연구의 결과임.

참고문헌

  1. GUL, S., AFTAB, N.. A Comparison between RISC and CISC Microprocessor Architectures. IJSEAT, North America, 4, jun. 2016. Available at: . Date accessed: 09 May. 2024.
  2. A. Waterman, K. Asanovi, and RISC-V International, "The RISC-V instruction set manual, Volume I: User-Level ISA, document version 20191213", 2019.
  3. Weicker, Reinhold P., "Dhrystone: A Synthetic Systems Programming Benchmark," Commun. ACM, vol. 27, no. 10, pp. 1013-1030, Oct.1984. [Online]. Available: http://doi.acm.org/10.1145/358274.358283
  4. EEMBC, "CoreMark - CPU Benchmark - MCU Benchmark," https://www.eembc.org/coremark/.
  5. S. Jo, J. Lee, Y. Kim, "A Design and Implementation of 32-bit Five-Stage RISC-V Processor Using FPGA", Journal of the Semiconductor & Display Technology, vol. 21, no. 4, pp. 27-32, 2022.
  6. A. Waterman, Y. Lee, D. Patterson, K. Asanovi, "The RISC-V Compressed Instruction Set Manual, document version 20151205", 2015
  7. T. Kanamori, H. Miyazaki, K. Kise, "RVCoreP-32IC: A high-performance RISC-V soft processor with an efficient fetch unit supporting the compressed instructions", Retrieved May, 6, 2024, from https://arxiv.org/abs/2011. 11246.
  8. D. Rossi, F. Conti, A. Marongiu, A. Pullini, I. Loi, M. Gautschi, G. Tagliavini, A. Capotondi, P. Flatresse, and L. Benini, "Pulp: A parallel ultra low power platform for next generation iot applications," in 2015 IEEE Hot Chips 27 Symposium (HCS), Aug 2015, pp. 1-39.
  9. SpinalHDL, "VexRiscv: A FPGA friendly 32 bit RISCV CPU implementation," https://github.com/ SpinalHD L/VexRiscv.
  10. H. Miyazaki, T. Kanamori , M. Ashraful Islam and K. Kise, "Rvcorep:An optimized risc-v soft processor of five-stage pipelining," arXiv preprint arXiv: 2002.03568, 2020.