과제정보
This research was funded by the National Research Foundation of Korea (NRF) grant funded by Korean Government (MIST) (No. 2022R1A4A3029433). The EDA tool was supported by the IC Design Education Center (IDEC)
DOI QR Code
개선된 게이트 바이어스 전압 구조를 갖춘 교차 결합 차동 정류기(Cross-Coupled Differential Rectifier, CCDR)를 제안한다. 제안된 정류기는 주요 정류 트랜지스터에 출력 연결 바이어스를 구현하여 도통 스윙을 증대시키는 추가적인 바이어스를 생성한다. 또한 게이트 단자는 정류기의 가장 낮은 노드와 병렬로 연결되어, 입력 전압을 제안된 게이트 바이어스 노드에 있는 특정 트랜지스터로 제어할 수 있게 한다. 이 설계는 이상적인 안테나를 사용하여 다양한 부하 및 매칭 네트워크 조건에서 시뮬레이션되어 정류기의 입력 임피던스를 맞추고 성능을 극대화한다. 제안된 기술은 28nm 공정을 사용하여 구현되었으며, 65.14%의 피크 변환 효율(PCE)을 달성하고, 다양한 부하에서 21 dBm 의 전체 동적 범위를 갖는다. 이 설계는 10㏀과 100pF 부하에서 0.8 V 의 출력을 생성하며, 동적 범위 내에서 최대 1.5 V 까지 확장될 수 있다.
This work presents a Cross-Coupled Differential Rectifier (CCDR) with an improved gate bias voltage topology, utilizing the rectifier's stage output-referred bias to increase the gate bias. The primary objective is to develop a 5.8 GHz rectifier operating at a much lower input power. The target input power is -10 dBm, which is insufficient to meet the threshold voltage of typical transistors (usually around 300 to 450 mV). Although the input power is inadequate to turn on the transistor fully, the transistor still generates a conduction swing as it operates in the sub-threshold region. Since the ratio of transconductance to current is very high in this region, an additional voltage bias is crucial to increase the swing and generate a higher output voltage. To achieve this, the proposed rectifier implements an output-connected bias for the main rectifying transistors, generating additional bias to enhance the conduction swing. Furthermore, the gate terminal is connected in parallel to the rectifier's lowest node, allowing the input voltage to be controlled by specific transistors on the proposed gate bias nodes. The design is simulated with an ideal antenna (with a 50 Ω antenna resistance) under various load and matching network conditions to match the rectifier's input impedance and maximize performance. The proposed technique, implemented using 28 nm technology, achieves a peak conversion efficiency (PCE) of 65.14%, with a total dynamic range of 21 dBm across various loads. The design generates an output of 0.8 V with a 10㏀ and 100pF load and can be extended within the dynamic range up to 1.5 V.
This research was funded by the National Research Foundation of Korea (NRF) grant funded by Korean Government (MIST) (No. 2022R1A4A3029433). The EDA tool was supported by the IC Design Education Center (IDEC)