• Transactions on Semiconductor Engineering
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• v.2 no.4
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• pp.13-20
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• 2024

This work presents a Cross-Coupled Differential Rectifier (CCDR) with an improved gate bias voltage topology, utilizing the rectifier's stage output-referred bias to increase the gate bias. The primary objective is to develop a 5.8 GHz rectifier operating at a much lower input power. The target input power is -10 dBm, which is insufficient to meet the threshold voltage of typical transistors (usually around 300 to 450 mV). Although the input power is inadequate to turn on the transistor fully, the transistor still generates a conduction swing as it operates in the sub-threshold region. Since the ratio of transconductance to current is very high in this region, an additional voltage bias is crucial to increase the swing and generate a higher output voltage. To achieve this, the proposed rectifier implements an output-connected bias for the main rectifying transistors, generating additional bias to enhance the conduction swing. Furthermore, the gate terminal is connected in parallel to the rectifier's lowest node, allowing the input voltage to be controlled by specific transistors on the proposed gate bias nodes. The design is simulated with an ideal antenna (with a 50 Ω antenna resistance) under various load and matching network conditions to match the rectifier's input impedance and maximize performance. The proposed technique, implemented using 28 nm technology, achieves a peak conversion efficiency (PCE) of 65.14%, with a total dynamic range of 21 dBm across various loads. The design generates an output of 0.8 V with a 10㏀ and 100pF load and can be extended within the dynamic range up to 1.5 V.