Transactions on Semiconductor Engineering (반도체공학회 논문지)

The Institute of Semiconductor Engineers (반도체공학회)
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Low Power Flip-Flop Circuit with a Minimization of Internal Node Transition

인터널 노드 변환을 최소화시킨 저전력 플립플롭 회로

  • Hyung-gyu Choi (Department of Semiconductor Science, Dongguk University) ;
  • Su-yeon Yun (Department of Semiconductor Science, Dongguk University) ;
  • Soo-youn Kim (Department of Semiconductor Science, Dongguk University) ;
  • Min-kyu Song (Department of Semiconductor Science, Dongguk University)
  • Received : 2023.09.20
  • Accepted : 2023.10.14
  • Published : 2023.10.31
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Abstract

This paper presents a low-power flip-flop(FF) circuit that minimizes the transition of internal nodes by using a dual change-sensing method. The proposed dual change-sensing FF(DCSFF) shows the lowest dynamic power consumption among conventional FFs, when there is no input data transition. From the measured results with 65nm CMOS process, the power consumption has been reduced by 98% and 32%, when the data activity is 0% and 100%, respectively, compared to conventional transmission gate FF(TGFF). Further, compared to change-sensing FF(CSFF), the power consumption of proposed DCSFF is smaller by 30%.

본 논문에서는 dual change-sensing 기법을 사용하여 내부 노드 변환을 최소화시킨 저전력 플립플롭 회로를 제안한다. 제안하는 Dual Change-Sensing Flip-Flop(DCSFF)은 데이터 변환이 존재하지 않는 경우, 기존에 존재하던 플립플롭들 중 동적 전력 소모가 가장 낮다. 65nm CMOS 공정을 사용한 측정 결과에 따르면, conventional Transmission Gate Flip-Flop(TGFF)와 비교하여 data activity 가 0% 와 100% 일때, 각각 98%와 32%의 감소된 전력 소모를 보였다. 또한 Change-Sensing Flip-lop(CSFF)과 비교하여 제안하는 DCSFF 는 30% 의 낮은 전력 소모를 보였다.

Keywords

Acknowledgement

본 연구는 산업통상자원부와 KSRC 지원 사업인 미래반도체소자 원천기술개발사업(#20019301)의 연구결과로 수행되었음. 또한, 본 연구의 칩 제작과 EDA Tool 은 IDEC 에서 지원받아 수행되었음.

References

  1. J. Yuan, C. Svensson, "High-Speed CMOS Circuit Technique," IEEE J. Solid-State Circuits, vol. 24, issue. 1, pp. 62-70, February, 1989. https://doi.org/10.1109/4.16303
  2. Jinuk Luke Shin et al., "The Next Generation 64b SPARC Core in a T4 SoC Processor," IEEE J. Solid-State Circuits, vol. 48, issue. 1, pp. 82-90, January, 2013. https://doi.org/10.1109/JSSC.2012.2223036
  3. D. Markovic, J. W. Tschanz, V. K. De, "Transmission-Gate Based Flip-Flop," U.S. Patent 6,642,765, 4, November, 2003.
  4. C. K. The, T. Fujita, H. Hara, M. Hamada, "A 77% Energy-Saving 22-Transistor Single-Phase Clocking D-Flip-Flop with Adaptive-Coupling Configuration in 40nm CMOS," In Proceedings of the 2011 IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, pp. 338-339, February, 2011.
  5. Y. Kim et al., "A static contention-free single-phase-clocked 24T flip-flop in 45nm for low-power applications," In Proceedings of the 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, USA, pp. 466-467, February, 2014.
  6. V. L. Le, A. Chang, T. T. Kim, "A 0.4-V, 0.138-fJ/cycle single-phase-clocking redundant-transition-free 24T flip-flop with change-sensing scheme in 40-nm CMOS," IEEE J. Solid-State Circuits, vol. 53, issue. 10, pp. 2806-2817, October, 2018. https://doi.org/10.1109/JSSC.2018.2863946
  7. M. Alioto, E. Consoli, G. Palumbo, "Variations in nanometer CMOS flip-flops: Part I-Impact of process variations on timing," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, issue. 8, pp. 2035-2043, August, 2015. https://doi.org/10.1109/TCSI.2014.2366811
  8. Y. Cai, A. Savanth, P. Prabhat, J. Myers, A. S. Weddell, T. J. Kazmierski, "Ultra-low power 18-transistor fully static contention-free single-phase clocked flip-flop in 65-nm CMOS," IEEE J. Solid-State Circuits, vol. 54, issue. 2, pp. 550-559, February, 2019. https://doi.org/10.1109/JSSC.2018.2875089
  9. N. Kawai et al., "A fully static topologically-compressed 21-transistor flip-flop with 75% power saving," In Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC), Singapore, December, 2013.
  10. V. L. Le, J. Li, A. Chang, T. T. Kim, "An 82% energy-saving change-sensing flip-flop in 40 nm CMOS for ultra-low power applications," In Proceedings of the 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC), Seoul, Korea (South), pp. 197-200, November, 2017.
  11. G. Shin, E. Lee, J. Lee, Y. Lee, Y. Lee, "A redundancy eliminated flip-flop in 28 nm for low-voltage low-power applications," IEEE Solid-State Circuits Letters, vol. 3, pp. 446-449, September, 2020. https://doi.org/10.1109/LSSC.2020.3025667
  12. Hari Kuamar P., Ramavenkateswaran N. "Low Power High Speed 15-Transistor Static True Single Phase Flip Flop," In Proceedings of the 2019 2nd International Conference on Intelligent Computing, Instrumentation and Control Technologies (ICICICT), Kannur, India, pp. 440-444, July, 2019.
  13. Y. Lee, G. Shin, Y. Lee, "A Fully Static True-Single-Phase-Clocked Dual-Edge-Triggered Flip-Flop for Near-Threshold Voltage Operation in IoT Applications," IEEE Access, vol. 8, pp. 40232-40245, February, 2020. https://doi.org/10.1109/ACCESS.2020.2976773
  14. Y. Huang, H. Jiao, "An Ultra-Low-Voltage Single-Phase Adaptive Pulse Latch with Redundant Toggling Elimination," In Proceedings of the 2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT), Kunming, China, pp. 1-3, November, 2020.
  15. G. Shin, E. Lee, J. Lee, Y. Lee, Y. Lee, "An Ultra-Low-Power Fully-Static Contention-Free Flip-Flop with Complete Redundant Clock Transition and Transistor Elimination," IEEE J. Solid-State Circuits, vol. 56, issue. 10, pp. 3039-3048, May, 2021. https://doi.org/10.1109/JSSC.2021.3077074
  16. L. Zhihong, Z. Yihao, H. Law, "Self-calibrate two-step digital setup/hold time measurement," In Proceedings of the 2010 International Symposium on VLSI Design, Automation and Test, Hsin Chu, Taiwan, pp. 232-235, April, 2010.
  17. B. Giridhar et al., "Pulse Amplification Based Dynamic Synchronizers with Meta-stability Measurement using Capacitance De-rating," In Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, San Jose, CA, USA, pp. 110-113, September, 2013.
  18. B. Zhai, R. G. Dreslinski, D. Blaauw, T. Mudge, D. Sylvester, "Energy efficient near-threshold chip multi-processing," In Proceedings of the 2007 International Symposium on Low Power Electronics and Design (ISLPED '07), Portland, OR, USA, pp. 32-37, August, 2007.
  19. A. Wang, B. H. Calhoun, A. P. Chandrakasan, "Sub-Threshold Design for Ultra Low-Power Systems," Springer, New York, NY, USA, 2006.