반도체디스플레이기술학회지 (Journal of the Semiconductor & Display Technology)

한국반도체디스플레이기술학회 (The Korean Society Of Semiconductor & Display Technology)
권호 표지

3.3kV SiC MOSFET 설계 및 제작을 위한 JFET 및 FLR 최적화 연구

A Study on JFET and FLR Optimization for the Design and Fabrication of 3.3kV SiC MOSFET

  • 강예환 (광운대학교 전자재료공학과) ;
  • 이현우 (광운대학교 전자재료공학과) ;
  • 구상모 (광운대학교 전자재료공학과)
  • YeHwan Kang (Department of Electronic Materials Engineering, Kwangwoon university) ;
  • Hyunwoo Lee (Department of Electronic Materials Engineering, Kwangwoon university) ;
  • Sang-Mo Koo (Department of Electronic Materials Engineering, Kwangwoon university)
  • 투고 : 2023.09.14
  • 심사 : 2023.09.18
  • 발행 : 2023.09.30
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초록

The potential performance benefits of Silicon Carbide(SiC) MOSFETs in high power, high frequency power switching applications have been well established over the past 20 years. In the past few years, SiC MOSFET offerings have been announced by suppliers as die, discrete, module and system level products. In high-voltage SiC vertical devices, major design concerns is the edge termination and cell pitch design Field Limiting Rings(FLR) based structures are commonly used in the edge termination approaches. This study presents a comprehensive analysis of the impact of variation of FLR and JFET region on the performance of a 3.3 kV SiC MOSFET during. The improvement in MOSFET reverse bias by optimizing the field ring design and its influence on the nominal operating performance is evaluated. And, manufacturability of the optimization of the JFET region of the SiC MOSFET was also examined by investigating full-map electrical characteristics.

키워드

과제정보

This work was supported by the Kwangwoon Univeristy in 2023, the Korea Institute for Advancement of Technology (KIAT) (P0012451) funded by the MOTIE and the Korea Evaluation Institute Of Industrial Technology (KEIT)(RS2022-00154720).

참고문헌

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