The Journal of the Korea institute of electronic communication sciences (한국전자통신학회논문지)

Korea Institute of Electronic Communication Science (한국전자통신학회)
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Design of In-Memory Computing Adder Using Low-Power 8+T SRAM

저 전력 8+T SRAM을 이용한 인 메모리 컴퓨팅 가산기 설계

  • Received : 2023.02.21
  • Accepted : 2023.04.17
  • Published : 2023.04.30
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Abstract

SRAM-based in-memory computing is one of the technologies to solve the bottleneck of von Neumann architecture. In order to achieve SRAM-based in-memory computing, it is essential to design efficient SRAM bit-cell. In this paper, we propose a low-power differential sensing 8+T SRAM bit-cell which reduces power consumption and improves circuit performance. The proposed 8+T SRAM bit-cell is applied to ripple carry adder which performs SRAM read and bitwise operations simultaneously and executes each logic operation in parallel. Compared to the previous work, the designed 8+T SRAM-based ripple carry adder is reduced power consumption by 11.53%, but increased propagation delay time by 6.36%. Also, this adder is reduced power-delay-product (PDP) by 5.90% and increased energy-delay- product (EDP) by 0.08%. The proposed circuit was designed using TSMC 65nm CMOS process, and its feasibility was verified through SPECTRE simulation.

SRAM 기반 인 메모리 컴퓨팅은 폰 노이만 구조의 병목 현상을 해결하는 기술 중 하나이다. SRAM 기반의 인 메모리 컴퓨팅을 구현하기 위해서는 효율적인 SRAM 비트 셀 설계가 필수적이다. 본 논문에서는 전력 소모를 감소시키고 회로 성능을 개선시키는 저 전력 차동 감지 8+T SRAM 비트 셀을 제안한다. 제안하는 8+T SRAM 비트 셀은 SRAM 읽기와 비트 연산을 동시에 수행하고 각 논리 연산을 병렬로 수행하는 리플 캐리 가산기에 적용한다. 제안하는 8+T SRAM 기반 리플 캐리 가산기는 기존 구조와 비교 하여 전력 소모는 11.53% 감소하였지만, 전파 지연 시간은 6.36% 증가하였다. 또한 이 가산기는 PDP(: Power Delay Product)가 5.90% 감소, EDP(: Energy Delay Product)가 0.08% 증가하였다. 제안한 회로는 TSMC 65nm CMOS 공정을 이용하여 설계하였으며, SPECTRE 시뮬레이션을 통해 타당성을 검증하였다.

Keywords

Acknowledgement

본 논문은 2022년도 정부(산업통상자원부)의 재원으로 한국산업기술진흥원의 지원을 받아 수행된 연구임(P0017011, 2022년 산업혁신인재성장지원사업)

References

  1. J. Chen, W. Zhao, Y. Wang, Y. Shu, W. Jiang and Y. Ha, "A Reliable 8T SRAM for High-Speed Searching and Logic-in-Memory Operations," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 30, no. 6, June 2022, pp. 769-780.  https://doi.org/10.1109/TVLSI.2022.3164756
  2. J. Chen, W. Zhao, Y. Wang and Y. Ha, "Analysis and Optimization Strategies Toward Reliable and High-Speed 6T Compute SRAM," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 4, April 2021, pp. 1520-1531.  https://doi.org/10.1109/TCSI.2021.3054972
  3. M. Nabavi and M. Sachdev, "A 290-mV, 3.34-MHz, 6T SRAM With pMOS Access Transistors and Boosted Wordline in 65-nm CMOS Technology," IEEE Journal of Solid-State Circuits, vol. 53, no. 2, Feb 2018, pp.656-667.  https://doi.org/10.1109/JSSC.2017.2747151
  4. J. P. Kulkarni, A. Goel, P. Ndai and K. Roy, "A Read-Disturb-Free, Differential Sensing 1R/1W Port, 8T Bitcell Array," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 9, Sept 2011, pp. 1727-1730.  https://doi.org/10.1109/TVLSI.2010.2055169
  5. K. Lee, J. Jeong, S. Cheon, W. Choi and J. Park, "Bit Parallel 6T SRAM In-memory Computing with Reconfigurable Bit-Precision," 2020 57th ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, 2020, pp. 1-6. 
  6. M. Nabavi and M. Sachdev, "A 290-mV, 3.34-MHz, 6T SRAM With pMOS Access Transistors and Boosted Wordline in 65-nm CMOS Technology," IEEE Journal of Solid-State Circuits, vol. 53, no. 2, Feb. 2018, pp. 656-667.  https://doi.org/10.1109/JSSC.2017.2747151
  7. A. Agrawal, A. Jaiswal, C. Lee and K. Roy, "X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 12, Dec. 2018, pp. 4219-4232.  https://doi.org/10.1109/TCSI.2018.2848999
  8. C. Yu, T. Yoo, K. T. C. Chai, T. T. -H. Kim and B. Kim, "A 65-nm 8T SRAM Compute-in-Memory Macro With Column ADCs for Processing Neural Networks."IEEE Journal of Solid-State Circuits, vol. 57, no. 11, Nov. 2022, pp.3466-3476.  https://doi.org/10.1109/JSSC.2022.3162602
  9. H. Kim, T. Yoo, T. T. -H. Kim and B. Kim, "Colonnade: A Reconfigurable SRAM-Based Digital Bit-Serial Compute-In-Memory Macro for Processing Neural Networks," IEEE Journal of Solid-State Circuits, vol. 56, no. 7, July 2021, pp. 2221-2233.  https://doi.org/10.1109/JSSC.2021.3061508
  10. S. Song, & Y. Kim, "Novel In-Memory Computing Adder Using 8+ T SRAM." Electronics, vol. 11, no. 6, March 2022.