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Thermal Design of High Power Semiconductor Using Insulated Metal Substrate

Insulated Metal Substrate를 사용한 고출력 전력 반도체 방열설계

  • Bongmin Jeong (Department of Electronic Engineering, Chungnam National University) ;
  • Aesun Oh (Electronics and Telecommunications Research Institute) ;
  • Sunae Kim (Electronics and Telecommunications Research Institute) ;
  • Gawon Lee (Department of Electronic Engineering, Chungnam National University) ;
  • Hyuncheol Bae (Electronics and Telecommunications Research Institute)
  • Received : 2023.03.08
  • Accepted : 2023.03.28
  • Published : 2023.03.30

Abstract

Today, the importance of power semiconductors continues to increase due to serious environmental pollution and the importance of energy. Particularly, SiC-MOSFET, which is one of the wide bandgap (WBG) devices, has excellent high voltage characteristics and is very important. However, since the electrical properties of SiC-MOSFET are heatsensitive, thermal management through a package is necessary. In this paper, we propose an insulated metal substrate (IMS) method rather than a direct bonded copper (DBC) substrate method used in conventional power semiconductors. IMS is easier to process than DBC and has a high coefficient of thermal expansion (CTE), which is excellent in terms of cost and reliability. Although the thermal conductivity of the dielectric film, which is an insulating layer of IMS, is low, the low thermal conductivity can be sufficiently overcome by allowing a process to be very thin. Electric-thermal co-simulation was carried out in this study to confirm this, and DBC substrate and IMS were manufactured and experimented for verification.

오늘날 심각한 환경 오염과 에너지의 중요성으로 전력 반도체의 중요도가 지속적으로 높아지고 있다. 특히 wide band gap(WBG)소자 중 하나인 SiC-MOSFET은 우수한 고전압 특성을 가지고 있어 그 중요도가 매우 높다. 하지만 SiC-MOSFET의 전기적 특성이 열에 민감하기 때문에 패키지를 통한 열 관리가 필요하다. 본 논문에서는 기존 전력 반도체에서 사용하는 direct bonded copper(DBC) 기판 방식이 아닌 insulated metal substrate(IMS) 방식을 제안한다. IMS는 DBC에 비해 공정이 쉬우며 coefficient of thermal expansion (CTE)가 높아서 비용과 신뢰성 측면에서 우수하다. IMS의 절연층인 dielectric film의 열전도도가 낮은 문제가 있지만 매우 얇은 두께로 공정이 가능하기 때문에 낮은 열 전도도를 충분히 극복할 수 있다. 이를 확인하기 위해서 이번 연구에서는 electric-thermal co-simulation을 수행하였으며 검증을 위해 DBC 기판과 IMS를 제작하여 실험하였다.

Keywords

Acknowledgement

This research was supported by National R&D Program through the National Research Foundation of Korea(NRF) funded by Ministry of Science and ICT (2022M318A1077243).

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