반도체디스플레이기술학회지 (Journal of the Semiconductor & Display Technology)

한국반도체디스플레이기술학회 (The Korean Society Of Semiconductor & Display Technology)
권호 표지

임베디드 환경에서의 32-bit RISC-V RV32IM 파이프라인 프로세서 설계 및 구현

A Design and Implementation of 32-bit RISC-V RV32IM Pipelined Processor in Embedded Systems

  • 박수빈 (상명대학교 시스템반도체공학과) ;
  • 김용우 (상명대학교 시스템반도체공학과)
  • Subin Park (Department of System Semiconductor Engineering, Sangmyung University) ;
  • Yongwoo Kim (Department of System Semiconductor Engineering, Sangmyung University)
  • 투고 : 2023.11.23
  • 심사 : 2023.12.14
  • 발행 : 2023.12.31
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초록

Recently, demand for embedded systems requiring low power and high specifications has been increasing, and RISC-V processors are being widely applied. RISC-V, a RISC-based open instruction set architecture (ISA), has been developed and researched by UC Berkeley and other researchers since 2010. RV32I ISA is sufficient to support integer operations such as addition and subtraction instructions, but M-extension should be defined for multiplication and division instructions. This paper proposes an RV32I, RV32IM processor, and indicates benchmark performance scores compared to an existing processor. Additionally, A non-stalling method was proposed to support a 2-stage pipelined DSP multiplier to the 5-stage pipelined RV32IM processor. Proposed RV32I and RV32IM processors satisfied a maximum operating frequency of 50 MHz on Artix-7 FPGA. The performance of the proposed processors was verified using benchmark programs from Dhrystone and Coremark. As a result, the Coremark benchmark results of the proposed processor showed that it outperformed the existing RV32IM processor by 23.91%.

키워드

과제정보

본 연구는 2023학년도 상명대학교 교내연구비를 지원받아 수행하였음.

참고문헌

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