Journal of the Semiconductor & Display Technology (반도체디스플레이기술학회지)

The Korean Society Of Semiconductor & Display Technology (한국반도체디스플레이기술학회)
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A Design and Implementation of 32-bit Five-Stage RISC-V Processor Using FPGA

FPGA를 이용한 32-bit RISC-V 5단계 파이프라인 프로세서 설계 및 구현

  • Jo, Sangun (Department of System Semiconductor Engineering, Sangmyung University) ;
  • Lee, Jonghwan (Department of System Semiconductor Engineering, Sangmyung University) ;
  • Kim, Yongwoo (Department of System Semiconductor Engineering, Sangmyung University)
  • 조상운 (상명대학교 시스템반도체공학과) ;
  • 이종환 (상명대학교 시스템반도체공학과) ;
  • 김용우 (상명대학교 시스템반도체공학과)
  • Received : 2022.11.01
  • Accepted : 2022.12.13
  • Published : 2022.12.31
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Abstract

RISC-V is an open instruction set architecture (ISA) developed in 2010 at UC Berkeley, and active research is being conducted as a processor to compete with ARM. In this paper, we propose an SoC system including an RV32I ISA-based 32-bit 5-stage pipeline processor and AHB bus master. The proposed RISC-V processor supports 37 instructions, excluding FENCE, ECALL, and EBREAK instructions, out of a total of 40 instructions based on RV32I ISA. In addition, the RISC-V processor can be connected to peripheral devices such as BRAM, UART, and TIMER using the AHB-lite bus protocol through the proposed AHB bus master. The proposed SoC system was implemented in Arty A7-35T FPGA with 1,959 LUTs and 1,982 flip-flops. Furthermore, the proposed hardware has a maximum operating frequency of 50 MHz. In the Dhrystone benchmark, the proposed processor performance was confirmed to be 0.48 DMIPS.

Keywords

Acknowledgement

본 연구는 2022학년도 상명대학교 교내연구비를 지원 받아 수행하였음.

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