전기전자학회논문지 (Journal of IKEEE)

  • 제25권1호
  • /
  • Pages.168-173
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  • 2021
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  • 1226-7244(pISSN)
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  • 2288-243X(eISSN)
한국전기전자학회 (Institute of Korean Electrical and Electronics Engineers)
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향상된 전기적 특성을 지닌 LVTSCR 기반의 N-Stack ESD 보호소자에 관한 연구

A Study on LVTSCR-Based N-Stack ESD Protection Device with Improved Electrical Characteristics

  • Jin, Seung-Hoo (Dept. of Electronics Engineering, Dankook University) ;
  • Woo, Je-Wook (Dept. of Electronics Engineering, Dankook University) ;
  • Joung, Jang-Han (Dept. of Electronics Engineering, Dankook University) ;
  • Koo, Yong-Seo (Dept. of Electronics Engineering, Dankook University)
  • 투고 : 2021.03.05
  • 심사 : 2021.03.26
  • 발행 : 2021.03.31
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초록

본 논문에서는 일반적인 ESD 보호소자인 LVTSCR의 구조적 변경을 통해 향상된 전기적 특성을 달성한 새로운 구조의 ESD 보호소자를 제안한다. 또한 요구되는 전압 Application에 따른 ESD Design Window에 최적화된 설계를 위하여 N-Stack 기술을 적용한다. 기존의 LVTSCR 구조에 추가로 삽입된 N-Well 영역은 Anode와 전기적으로 연결함으로써 추가적인 ESD 방전경로를 제공하고 이는 온-저항 및 온도 특성을 향상시킨다. 또한 짧은 Trigger 경로는 기존의 LVTSCR보다 더 낮은 Trigger Voltage 가지므로 우수한 Snapback 특성을 지닌다. 그리고 제안된 ESD 보호소자의 전기적 특성을 검증하기 위해 Synopsys 사의 T-CAD Simulator을 이용하였다.

In this paper, we propose a new structure of ESD protection device that achieves improved electrical characteristics through structural change of LVTSCR, which is a general ESD protection device. In addition, it applies N-Stack technology for optimized design in the ESD Design Window according to the required voltage application. The N-Well area additionally inserted in the existing LVTSCR structure provides an additional ESD discharge path by electrically connecting to the anode, which improves on-resistance and temperature characteristics. In addition, the short trigger path has a lower trigger voltage than the existing LVTSCR, so it has excellent snapback characteristics. In addition, Synopsys' T-CAD Simulator was used to verify the electrical characteristics of the proposed ESD protection device.

키워드

참고문헌

  1. C. Y. Lin, Y. H. Wu, and M. D. Ker, "Low-leakage and low-trigger-voltage SCR device for ESD protection in 28nm high-k metal gate CMOS process," IEEE Electron Device Lett., vol.37, no.11, pp,1387-1390, 2016. DOI: 10.1109/LED.2016.2608721
  2. Z. Wang, R. C. Sun, J. Liou, and D. G. Liu, "Optimized pMOS-triggered bidirectional SCR for low-voltage ESD protection applications," IEEE Trans. Electron Device, vol.61, no.7 pp. 2588-2594, 2014. DOI: 10.1109/TED.2014.2320827
  3. Y. C. Huang and M. D. Ker, "A latchup-immune and robust SCR device for ESD protection in 0.25-um 5-V CMOS Process," IEEE Electron Device Lett., vol.34, no.5, pp.674-676, 2013. DOI: 10.7471/ikeee.2020.24.3.890
  4. A. Chatterjee and T. Polgreen, "A low-voltage triggering SCR for on-chip ESD protection at ouput and input pads," IEEE Electron Device Lett., vol.12, pp.21-22, 1991. DOI: 10.1109/VLSIT.1990.111015
  5. V. A. Vashchenko, A. Concannon, M. T. Beek and P. Hopper, "High holding voltage cascoded LVTSCR structures for 5.5-V tolerant ESD protection clamps," IEEE Transactions on Device and Materials Reliability, vol.4, no.2 pp.273-280, 2004. DOI: 10.1109/TDMR.2004.826584
  6. M. D. Ker, C. H. Chang, "Stacked-NMOS triggered silicon-controlled rectifier for ESD protection in high/low-voltage-tolerant I/O interface," IEEE Electron Device Lett., vol.23, no.6, pp.363-365, 2002. DOI: 10.1109/LED.2002.1004236