전기전자학회논문지 (Journal of IKEEE)

  • 제25권1호
  • /
  • Pages.15-24
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  • 2021
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  • 1226-7244(pISSN)
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  • 2288-243X(eISSN)
한국전기전자학회 (Institute of Korean Electrical and Electronics Engineers)
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스위칭 손실을 줄인 1700 V 4H-SiC Double Trench MOSFET 구조

A Novel 1700V 4H-SiC Double Trench MOSFET Structure for Low Switching Loss

  • Na, Jae-Yeop (Dept. of Electronics Engineering, Sogang University) ;
  • Jung, Hang-San (Dept. of Electronics Engineering, Sogang University) ;
  • Kim, Kwang-Su (Dept. of Electronics Engineering, Sogang University)
  • 투고 : 2021.02.10
  • 심사 : 2021.03.24
  • 발행 : 2021.03.31
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⟨ 이전 논문 다음 논문 ⟩

초록

본 논문에서는 CDT(Conventional Double Trench) MOSFET보다 스위칭 시간과 손실이 적은 1700 V EPDT(Extended P+ shielding floating gate Double Trench) MOSFET 구조를 제안하였다. 제안한 EPDT MOSFET 구조는 CDT MOSFET에서 소스 Trench의 P+ shielding 영역을 늘리고 게이트를 N+와 플로팅 P- 폴리실리콘 게이트로 나누었다. Sentaurus TCAD 시뮬레이션을 통해 두 구조를 비교한 결과 온 저항은 거의 차이가 없었으나 Crss(게이트-드레인 간 커패시턴스)는 게이트에 0 V 인가 시에는 CDT MOSFET 대비 32.54 % 줄었고 7 V 인가 시에는 65.5 % 감소하였다. 결과적으로 스위칭 시간 및 손실은 각각 45 %, 32.6 % 줄어 스위칭 특성이 크게 개선되었다.

In this paper, 1700 V EPDT (Extended P+ shielding floating gate Double Trench) MOSFET structure, which has a smaller switching time and loss than CDT (Conventional Double Trench) MOSFET, is proposed. The proposed EPDT MOSFET structure extended the P+ shielding area of the source trench in the CDT MOSFET structure and divided the gate into N+ and floating P- polysilicon gate. By comparing the two structures through Sentaurus TCAD simulation, the on-resistance was almost unchanged, but Crss (Gate-Drain Capacitance) decreased by 32.54 % and 65.5 %, when 0 V and 7 V was applied to the gate respectively. Therefore, the switching time and loss were reduced by 45 %, 32.6 % respectively, which shows that switching performance was greatly improved.

키워드

참고문헌

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