Journal of IKEEE (전기전자학회논문지)

Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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2048-point Low-Complexity Pipelined FFT Processor based on Dynamic Scaling

동적 스케일링에 기반한 낮은 복잡도의 2048 포인트 파이프라인 FFT 프로세서

  • Kim, Ji-Hoon (Dept. of Electrical and Information Eng., SeooulTech)
  • Received : 2021.12.20
  • Accepted : 2021.12.27
  • Published : 2021.12.31
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Abstract

Fast Fourier Transform (FFT) is a major signal processing block being widely used. For long-point FFT processing, usually more than 1024 points, its low-complexity implementation becomes very important while retaining high SQNR (Signal-to-Quantization Noise Ratio). In this paper, we present a low-complexity FFT algorithm with a simple dynamic scaling scheme. For the 2048-point pipelined FFT processing, we can reduce the number of general multipliers by half compared to the well-known radix-2 algorithm. Also, the table size for twiddle factors is reduced to 35% and 53% compared to the radix-2 and radix-22 algorithms respectively, while achieving SQNR of more than 55dB without increasing the internal wordlength progressively.

고속 푸리에 변환(Fast Fourier Transform, FFT)은 다양한 응용처에서 널리 사용되는 주요 신호처리 블록이다. 일반적으로 1024 포인트 이상의 긴 FFT 처리의 경우 높은 SQNR(Signal-to-Quantization Ratio)를 유지하면서도 낮은 하드웨어 복잡도의 구현이 매우 중요하다. 본 논문에서는 낮은 복잡도의 FFT 알고리즘과 간단한 동적스케일링 기법을 제시한다. 이를 통해 2048 포인트 FFT연산에 대해서 널리 알려진 radix-2 알고리즘에 비해 곱셉기의 수를 절반으로 줄일 수 있으며, 또한 twiddle factor를 저장하기 위해 필요한 테이블의 크기를 radix-2 및 radix-22 알고리즘에 비해 각각 35% 및 53%로 축소할 수 있다. 그리고 내부 데이터의 폭을 점진적으로 늘리지 않고서도 55dB 이상의 높은 SQNR을 달성하는 것을 확인하였다.

Keywords

Acknowledgement

This study was financially supported by Seoul National University of Science and Technology.

References

  1. S. He and M. Torkelson, "Design and Implementation of a 1024-point pipeline FFT processor," in Proc. IEEE Custom Integrated Circuits. Conf., pp.131-134, 1998. DOI: 10.1109/CICC.1998.694922
  2. S. He and M. Torkelson, "Designing pipeline FFT processor for OFDM (de)modulation," in Proc. IEEE URSI Int. Symp. Signals, Syst. Electron., pp. 257-262, 1998. DOI: 10.1109/ISSSE.1998.738077
  3. L. Pang, et al., "Design and Implementation of High Performance FFT Processor with Radix-2k Algorithm," in Proc. IEEE International Conference on Signal, Information and Data Processing, 2019. DOI: 10.1109/ICSIDP47821.2019.9173055
  4. J. W. Cooley and J. W. Tukey, "An algorithm for the machine computation of the complex Fourier series," Math. Computation. vol.19, pp.297-301, 1965. DOI: 10.1090/S0025-5718-1965-0178586-1
  5. I. C. Park, W. H. Son, and J. H. Kim., "Twiddle Factor Transformation for Pipelined FFT Processing," in Proc. IEEE International Conference on Computer Design, 2007. DOI: 10.1109/ICCD.2007.4601872
  6. T. Nguyen and H. Lee, "Shared CSD complex constant multiplierfor parallel FFT processors," in Proc. International SoC Design Conference, 2015. DOI: 10.1109/ISOCC.2015.7401648
  7. Y. W. Lin, H. Y. Liu and C. Y. Lee, "A 1-GS/s FFT/IFFT Processor for UWB Applications," IEEE J. Solid-State Circuits, vol.40, no.8, pp.1726-1735, 2005. DOI: 10.1109/JSSC.2005.852007
  8. David Elam and Cesar Iovescu, "A Block Floating Point Implementation for an N-Point FFT on the TMS320C55x DSP," Application Report, SPRA948, Texas Instruments, 2003.