• Journal of IKEEE
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• v.25 no.4
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• pp.697-702
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• 2021

Fast Fourier Transform (FFT) is a major signal processing block being widely used. For long-point FFT processing, usually more than 1024 points, its low-complexity implementation becomes very important while retaining high SQNR (Signal-to-Quantization Noise Ratio). In this paper, we present a low-complexity FFT algorithm with a simple dynamic scaling scheme. For the 2048-point pipelined FFT processing, we can reduce the number of general multipliers by half compared to the well-known radix-2 algorithm. Also, the table size for twiddle factors is reduced to 35% and 53% compared to the radix-2 and radix-2² algorithms respectively, while achieving SQNR of more than 55dB without increasing the internal wordlength progressively.

• The Journal of the Acoustical Society of Korea
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• v.2 no.1
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• pp.41-47
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• 1983

고속 Walsh-hadamard 변환방식을 사용하여 근사적으로 조기적인 신호의 μPCM 데이터를 압축 할 수 있음을 확인하였으며 최대 압축율은 기준 SQNR을 30dB로 할 경우 6 이상임을 보였다. 또한 decion level을 변화시킬 때 SQNR 변화를 조사하였으며 시스템 특성에 다라 decion level의 최적화를 얻을 수 있었다. 또한 양자화 레벨을 조정하여 SQNR을 검토한 바 대체로 선형적임을 나타내었다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.9 no.3
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• pp.120-126
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• 1984

In this paper, there is presented the novel encoder circuit design method in the realization of exponential adaption process on the delta modulation coding of speech signals. The digital implementation has been adapted for the illustration of above, especially using a rate multiplier end a double integration circuit. The use of a double integration of the local decoder included in the ADM encoder in prove the undesirable characteristics which the low switching speed of the ratemultiplier couses the SQNR to decreuse, and the SQNR of the decoding signal by above realization is relatively uniformed in wide range of signal levels. The validity of the above design is verified by laboratory experiments.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.10C
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• pp.963-972
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• 2002

An 8192-point pipelined FFT/IFFT processor core is designed, which can be used in multi-carrier modulation systems such as DUf-based VDSL modem and OFDM-based DVB system. In order to improve the signal-to-quantization-noise ratio (SQNR) of FFT/IFFT results, two-step convergent block floating-point (TS_CBFP) scaling is employed. Since the proposed TS_CBFP scaling does not require additional buffer memory, it reduces memory as much as about 80% when compared with conventional CBFP methods, resulting in area-and power-efficient implementation. The SQNR of about 60-㏈ is achieved with 10-bit input, 14-bit internal data and twiddle factors, and 16-bit output. The core synthesized using 0.25-$\mu\textrm{m}$ CMOS library has about 76,300 gates, 390K bits RAM, and twiddle factor ROM of 39K bits. Simulation results show that it can safely operate up to 50-㎒ clock frequency at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every 164-${\mu}\textrm{s}$. It was verified by Xilinx FPGA implementation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.11 no.6
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• pp.411-420
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• 1986

Quantization noise of nonadaptive Linear Delta Modulation(LDM) and adaptive Constant Factor Delta Modulation(CFDM) systems is studied. The formulas for quantization noise of CFDM system are derived on the basis of the rusults of LDM. And the output signal-to-quantization noise ratios(SNR) in LDM and CFDM systems are calculated in the range of bit rates from 16[Kb/s] to 96[Kb/s]. By comparing LDM and CFDM, it is known that the adaptive DM is superior to non-adaptive DM by 8[dB] when bit rate is 20[Kb/s] and SNR advantage increases to 14[dB] when bit rate is 56[Kb/s]. All the theoretical results agree well with the experimental results.

• The Journal of the Acoustical Society of Korea
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• v.9 no.6
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• pp.5-13
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• 1990

본 논문에서는 16Kbps 및 32 Kbps 전송속도에서 ADM의 음질을 개선하기 위하여 두 가지 방 식을 적용한다. 첫째로, 고차 예측기 또는 적응 예측기를 ADM에 활용한다. ADM의 경우에 2차 또는 3 차 예측기를 사용하면 16Kbps 전송속도에서는 별로 개선이 없지만 32Kbps 전송속도에서는 SQNR\sub SEG\척도로 약 3-4dB의 상당한 이득이 얻어진다. 또한 ADM에 적응 예측기를 활용하면 최대 성능은 SZNR\sub SEG\ dir 2dB 정도 개선되지만 양자화 잡음의 축적 때문에 동작 범위가 매우 좁아진다. 둘 째로, 지연 결정 방식을 ADM에 이용한다. 지연 결정 방식을 2차 예측기를 갖고 있는 ADM에 적용하면 약 2dB 정도 개선되지만 양자화 잡음의 축적 때문에 동작 범위가 매우 좁아진다. 둘째로 지연 결정 방 식을 ADM 에 이용한다. 지연 결정 방식을 2차 예측기를 갖고 있는 ADM에 적용하면 1차 예측기를 갖 고 있는 ADMDP 적용했을 때 보다 16또는 32Kbps일 때 SQNR\sub SEG\척도로 재래의 ADM 보다 약 5dB 정도의 성능 개선이 얻어진다.

• Proceedings of the KIEE Conference
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• 2003.07d
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• pp.2783-2785
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• 2003

In multi-dimensional magnetic resonance imaging, data is obtained in the spatial frequency domain. Since the signal variation in the spatial frequency domain is much larger than that in the spatial domain, analog-to-digital converts with wide conversion bits are required. In this paper, the quantization noise in magnetic resonance imaging is analyzed. The signal-to-quantization noise ratio(SQNR) in the reconstructed image is derived from the level of quantization in the data acquisition. Since the quantization noise is proportional to the signal amplitude, it becomes more dominant in high field imaging. Using the derived formula the SQNR for several MRI systems are evaluated, and it is shown that the quantization noise can be a limiting factor in high field imaging, especially in three dimensional imaging in magnetic resonance imaging.

• Journal of Biomedical Engineering Research
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• v.28 no.3
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• pp.429-440
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• 2007

A coded excitation has been studied to improve the performance for ultrasound imaging in term of SNR, imaging frame rate, contrast to tissue ratio, and so forth. However, it requires a complicated arbitrary waveform transmitter for each active channel that is typically composed of a multi-bit Digital-to-Analog Converter (DAC) and a linear power amplifier (LPA). Not only does the LPA increase the cost and size of a transmitter block, but it consumes much power, increasing the system complexity further and causing a heating-up problem. This paper proposes an optimized 1.5bit fourth order sigma-delta modulation technique applicable to design an efficient arbitrary waveform generator with greatly reduced power dissipation and hardware. The proposed SDM can provide a required SQNR with a low over-sampling ratio of 4. To this end, the loop coefficients are optimized to minimize the quantization noise power in signal band while maintaining system stability. In addition, the decision level for the 1.5 bit quantizer is optimized for a given input waveform, which results in the SQNR improvement of more than 5dB. Computer simulation results show that the SQNR of a FM(frequency modulated) signal generated by using the proposed method is about 26dB, and the peak side-lobe level (PSL) of its compressed waveform on receive is -48dB.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.2A
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• pp.209-215
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• 2010

This paper describes a design of variable-length FFT/IFFT processor (VL_FCore) for OFDM-based multi-standard communication systems. The VL_FCore adopts in-place single-memory architecture, and uses a hybrid structure of radix-4 and radix-2 DIF algorithms to accommodate various FFT lengths in the range of $N=64{\times}2^k\;(0{\leq}k{\leq}7)$. To achieve both memory size reduction and the improved SQNR, a two-step conditional scaling technique is devised, which conditionally scales the intermediate results of each computational stage. The performance analysis results show that the average SQNR's of 64~8,192-point FFT's are over 60-dB. The VL_FCore synthesized with a $0.35-{\mu}m$ CMOS cell library has 23,000 gates and 32 Kbytes memory, and it can operate with 75-MHz@3.3-V clock. The 64-point and 8,192-point FFT's can be computed in $2.25-{\mu}s$ and $762.7-{\mu}s$, respectively, thus it satisfies the specifications of various OFDM-based systems.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.11
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• pp.33-40
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• 2005

This paper describes a design of FFT/IFFT Core(FFT256/2k), which is an essential block in terrestrial DMB modem. It has four operation modes including 256/512/1024/2048-point FFT/IFFT in order to support the Eureka-147 transmission modes. The hybrid architecture, which is composed of R2SDF and R2SDC structure, reduces memory by $62\%$ compared to R2SDC structure, and the SQNR performance is improved by TS_CBFP(Two Step Convergent Block Floating Point). Timing simulation results show that it can operate up to 50MHz(a)2.5-V, resulting that a 2048-point FFT/IFFT can be computed in 41-us. The FFT256/2k core designed in Verilog-HDL has about 68,400 gates and 58,130 RAM. The average power consumption estimated using switching activity is about 113-mW, and the total average SQNR of over 50-dB is achieved. The functionality of the core was fully verified by FPGA implementation.