Journal of Power Electronics

The Korean Institute of Power Electronics (전력전자학회)
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Design and Verification of Improved Cascaded Multilevel Inverter Topology with Asymmetric DC Sources

  • Tarmizi, Tarmizi (Department of Electrical Engineering, Faculty of Engineering, Syiah Kuala University) ;
  • Taib, Soib (School of Electrical and Electronics Engineering, USM Engineering Campus) ;
  • Desa, M.K. Mat (School of Electrical and Electronics Engineering, USM Engineering Campus)
  • Received : 2018.11.06
  • Accepted : 2019.04.19
  • Published : 2019.09.20
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Abstract

This paper presents the design and implementation of an improved cascaded multilevel inverter topology with asymmetric DC sources. This experimental inverter topology is a stand-alone system with simulations and experiments performed using resistance loads. The topology uses four asymmetric binary DC sources that are independent from each other and one H-bridge. The topology was simulated using PSIM software before an actual prototype circuit was tested. The proposed topology was shown to be very efficient. It was able to generate a smooth output waveform up to 31 levels with only eight switches. The obtained simulation and experimental results are almost identical. In a 1,200W ($48.3{\Omega}$) resistive load application, the THDv and efficiency of the topology were found to be 1.7% and 97%, respectively. In inductive load applications, the THDv values were 1.1% and 1.3% for an inductive load ($R=54{\Omega}$ dan L=146mH) and a 36W fluorescent lamp load with a capacitor connected at the dc bus.

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References

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