3차원 플래시 메모리의 전하 손실 원인 규명을 위한 Activation Energy 분석

Study on the Activation Energy of Charge Migration for 3D NAND Flash Memory Application

  • Yang, Hee Hun (Dept. of Electronics Engineering, Chungnam National University) ;
  • Sung, Jae Young (Dept. of Electronics Engineering, Chungnam National University) ;
  • Lee, Hwee Yeon (Dept. of Electronics Engineering, Chungnam National University) ;
  • Jeong, Jun Kyo (Dept. of Electronics Engineering, Chungnam National University) ;
  • Lee, Ga won (Dept. of Electronics Engineering, Chungnam National University)
  • 투고 : 2019.06.19
  • 심사 : 2019.06.22
  • 발행 : 2019.06.30

초록

The reliability of 3D NAND flash memory cell is affected by the charge migration which can be divided into the vertical migration and the lateral migration. To clarify the difference of two migrations, the activation energy of the charge loss is extracted and compared in a conventional square device pattern and a new test pattern where the perimeter of the gate is exaggerated but the area is same. The charge loss is larger in the suggested test pattern and the activation energy is extracted to be 0.058 eV while the activation energy is 0.28 eV in the square pattern.

키워드

참고문헌

  1. Wang, Chih Hsin, and P-F. Zhang. "Three-dimensional DIBL for shallow-trench isolated MOSFET's." IEEE Transactions on Electron Devices, Vol. 46, pp.139-144, 1999. https://doi.org/10.1109/16.737452
  2. Gupta, Deepika, and Santosh Kumar Vishvakarma. "Improved short-channel characteristics with long data retention time in extreme short-channel flash memory devices." IEEE Transactions on Electron Devices, Vol. 63, pp. 668-674, 2016. https://doi.org/10.1109/TED.2015.2510018
  3. Uren, M. J., et al. "Punch-through in short-channel AlGaN/GaN HFETs." IEEE Transactions on Electron Devices, Vol. 53, pp.395-398, 2006. https://doi.org/10.1109/TED.2005.862702
  4. Hoefler, Alexander B., et al. "Non-volatile memory device having an anti-punch through (APT) region." U.S. Patent No. 6,713,812. 30 Mar. 2004.
  5. Song, Ihun, et al. "Short channel characteristics of gallium-indium-zinc-oxide thin film transistors for three-dimensional stacking memory." IEEE Electron Device Letters, Vol. 29, pp.549-552, 2008. https://doi.org/10.1109/LED.2008.920965
  6. Bohara, Pooja, and Santosh Kumar Vishvakarma. "NAND flash memory device with ground plane in buried oxide for reduced short channel effects and improved data retention." Journal of Computational Electronics Vol.18, pp.500-508, 2019. https://doi.org/10.1007/s10825-018-01298-9
  7. Lu, Chih-Yuan, Kuang-Yeu Hsieh, and Rich Liu. "Future challenges of flash memory technologies." Microelectronic engineering, Vol. 86, No.3, pp.283-286, 2009. https://doi.org/10.1016/j.mee.2008.08.007
  8. Lo, S-H., Douglas A. Buchanan, and Yuan Taur. "Modeling and characterization of quantization, polysilicon depletion, and direct tunneling effects in MOSFETs with ultrathin oxides." IBM Journal of Research and Development, Vol. 43, pp.327-337, 1999. https://doi.org/10.1147/rd.433.0327
  9. Kim, Hyunsuk, et al. "Evolution of NAND flash memory: From 2D to 3D as a storage market leader." 2017 IEEE International Memory Workshop (IMW). IEEE, pp.1-4, 2017.
  10. Sangyong Park, "Three dimensional simulation of retention characteristics of Charge Trap (CT) NAND Flash memory." SEOUL NATIONAL UNIVERSITY, 2013.
  11. Jun Ha Lee, Hoong Joo Lee, "Three-Dimensional Analysis of Self-Heating Effects in SOI Device." Journal of the Semiconductor & Display Equipment Technology, Vol.3, No.4, 2004.