Fig. 1 block diagram of a dual-mode power amplifier:(a) split power stage and (b) bypass structures.
Fig. 2 Simple schematic of proposed driver stage for bypass structure.
Fig. 3 Simple schematic of dual-mode CMOS power amplifier using proposed bypass structure.
Fig. 4 Layout of the designed three-port transformer.
Fig. 5 Simulation results of ZL,High and ZL,Low.
Fig. 6 Chip photograph of the designed power amplifier.
Fig. 7 Measured current consumption according to the output power.
Fig. 8 Measured gain and PAE according to the output power.
참고문헌
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피인용 문헌
- 1.9-GHz CMOS Power Amplifier using Adaptive Biasing Technique at AC Ground vol.17, pp.4, 2019, https://doi.org/10.6109/jicce.2019.17.4.285