The Transactions of The Korean Institute of Electrical Engineers (전기학회논문지)

The Korean Institute of Electrical Engineers (대한전기학회)
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Low Power SAR ADC with Series Capacitor DAC

직렬 커패시터 D/A 변환기를 갖는 저전력 축차 비교형 A/D 변환기

  • Lee, Jeong-Hyeon (Dept. of Electronic Engineering, Chonbuk National University) ;
  • Jin, Yu-Rin (Dept. of Electronic Engineering, Chonbuk National University) ;
  • Cho, Seong-Ik (Dept. of Electronic Engineering, Chonbuk National University)
  • Received : 2018.08.31
  • Accepted : 2018.12.17
  • Published : 2019.01.01
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Abstract

The charge redistribution digital-to-analog converter(CR-DAC) is often used for successive approximation register analog-to-digital converter(SAR ADC) that requiring low power consumption and small circuit area. However, CR-DAC is required 2 to the power of N unit capacitors to generate reference voltage for successive approximation of the N-bit SAR ADC, and many unit capacitors occupy large circuit area and consume more power. In order to improve this problem, this paper proposes SAR ADC using series capacitor DAC. The series capacitor DAC is required 2(1+N) unit capacitors to generate reference voltage for successive approximation and charges only two capacitors of the reference generation block. Because of these structural characteristics, the SAR ADC using series capacitor DAC can reduce the power consumption and circuit area. Proposed SAR ADC was designed in CMOS 180nm process, and at 1.8V supply voltage and 500kS/s sampling rate, proposed 6-bit SAR ADC have signal-to-noise and distortion ratio(SNDR) of 36.49dB, effective number of bits(ENOB) of 5.77-bit, power consumption of 294uW.

Keywords

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그림 1 전하 재분배 DAC를 이용한 SAR ADC Fig. 1 SAR ADC using charge redistribution DAC

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그림 2 전하 재분배 DAC의 출력 Fig. 2 Output of the charge redistribution DAC

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그림 3 커패시터들의 직렬연결을 이용한 직렬 커패시터 DAC Fig. 3 Series capacitor DAC using series connection of capacitors

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그림 4 전치 증폭기를 가지는 동적 비교기 Fig. 4 Dynamic comparator with preamplifier

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그림 5 제안하는 6-bit SAR ADC를 위한 직렬 커패시터 DAC의 제어 신호들 Fig. 5 Control signals of the series capacitor DAC for proposed 6-bit SAR ADC

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그림 6 중첩된 제어 신호의 예시 Fig. 6 Example of overlapped control signals

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그림 7 중첩된 제어 신호가 인가된 직렬 커패시터 DAC의 동작 Fig. 7 Operation of the series capacitor DAC withoverlapped control signals applied

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그림 8 동적 특성 모의실험을 위한 전력 스펙트럼 밀도 Fig. 8 PSD for dynamic characteristics simulation

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그림 9 DNL과 INL의 모의실험 결과 Fig. 9 Simulation results of DNL and INL

표 1 제안하는 SAR ADC와 이전 연구들의 성능 비교 Table 1 Comparison of performance between proposed SAR ADC and previous studies

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표 2 DAC에 따른 단위 커패시터의 수 비교 Table 2 Comparison of the number of unit capacitors according to the DAC

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References

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