Journal of the Korea Society of Computer and Information (한국컴퓨터정보학회논문지)

Korean Society of Computer Information (한국컴퓨터정보학회)
권호 표지
DOI QR코드

DOI QR Code

A Compact Representation of Translation Pages for Flash Translation Layers of Solid State Drives

  • Kim, Yong-Seok (Department of Computer and Communications Engineering, Kangwon National University)
  • Received : 2018.07.24
  • Accepted : 2018.10.27
  • Published : 2019.02.28
Download PDF
⟨ Previous Next ⟩

Abstract

This paper presents CTP (Compact Translation Page), a compact representation of translation pages, for page mapping-based flash translation layers to improve RAM utilization and reduce the response time of solid state drives. CTP can store translation information twice in a translation page and the total number of translation pages stored in flash is reduced to half. Therefore, CTP halves the RAM size of the directory of translation pages and uses the saved RAM space for translation cache. CTP shows the best response time when compared to existing page mapping-based flash translation layers.

Keywords

CPTSCQ_2019_v24n2_1_f0001.png 이미지

Fig. 1. Two Level Structure of Address Translation

CPTSCQ_2019_v24n2_1_f0002.png 이미지

Fig. 2. Translation of LPN to PPN

CPTSCQ_2019_v24n2_1_f0003.png 이미지

Fig. 3. Representation of Translation pages

CPTSCQ_2019_v24n2_1_f0004.png 이미지

Fig. 4. Comparison of Response Times

CPTSCQ_2019_v24n2_1_f0006.png 이미지

Fig. 5. Response Time According to RAM Size (Financial 1)

Table 1. Characteristics of Traces

CPTSCQ_2019_v24n2_1_t0001.png 이미지

Table 2. Average Number of Valid Pages on Block Merge

CPTSCQ_2019_v24n2_1_t0002.png 이미지

References

  1. S. Lee, D. Park, T. Chung, D. Lee, S. Park, H. Song, "A log buffer based flash translation layer using fully associative sector translation," ACM Trans. Embedded Computing Sys. Vol. 6, No. 3, pp. 1-27, 2007. https://doi.org/10.1145/1210268.1216577
  2. Samsung 1G x 8 bit - 2G x 8 bit- 4G x 8 bit NAND flash memory datasheet (K9XXG08UXA), https://www.scribd.com/document/ 7010323/Samsung-1G-x-8-Bit-2G-x-8-Bit-4G-x-8-Bit-NAND-Flash-Memory-Datasheet
  3. J. Kim, J. M. Kim, S. H. Hoh, S. L. Min, and Y. Cho, "A Space Efficient flash translation layer for CompactFlash system," IEEE Trans. Consum. Electron., vol. 48, no. 2, pp. 366-375, May 2002. https://doi.org/10.1109/TCE.2002.1010143
  4. S.-W. Lee, D.-J. Park, et al., "A log buffer-based flash translation layer using fully-associative sector translation," ACM Trans. Emb. Comput. Syst., vol. 6, no. 3, pp. 1-27, Jul. 2007. https://doi.org/10.1145/1210268.1216577
  5. J.-U. Kang, H. Jo, J.-S. Kim, and J. Lee, "A superblock-based flash translation layer for NAND flash memory," in Proc. 6th ACM IEEE Int. Conf. Embedded Softw., pp. 161-170, Oct. 2006
  6. Y. Guan, et. al., "A Block-Level Log-Block Management Scheme for MLC NAND Flash Memory Storage Systems," IEEE Trans. on Computers, vol. 66, no. 9, pp. 1464-1477, Sep. 2017. https://doi.org/10.1109/TC.2017.2679180
  7. A. Gupta, Y. Kim, and B. Urgaonkar, "DFTL: A flash translation layer employing demand-based selective caching of page-level address mappings," in Proc. 14th Int. Conf. Archit. Support Program. Languages Operating Syst., pp. 229-240, 2009.
  8. H.-P. Choi, Y.-S. Kim, "An Efficient Cache Management Scheme of Flash Translation Layer for Large Size Flash Memory Drives," Journal of The Korea Society of Computer and Information Vol. 20 No. 11, pp. 31-38, November 2015 https://doi.org/10.9708/jksci.2015.20.11.031
  9. Storage Traces of UMass Trace Repository, http://traces.cs.umass.edu/index.php/Storage/Storage
  10. D. Park, B. Debnath, and D. Du, "CFTL: An Adaptive Hybrid Flash Translation Layer with Efficient Caching Strategies," IEEE Trans. on Computers, pp. 1-15, Sep. 2011.

Cited by

  1. SSD FTL의 캐시 메커니즘에 대한 심층 분석 및 개선 vol.15, pp.1, 2020, https://doi.org/10.14372/iemek.2020.15.1.9