[KSCI] Korea Science Citation Index Service

http://dx.doi.org/10.9708/jksci.2019.24.02.001

A Compact Representation of Translation Pages for Flash Translation Layers of Solid State Drives

Kim, Yong-Seok (Department of Computer and Communications Engineering, Kangwon National University)

Publication Information

Journal of the Korea Society of Computer and Information / v.24, no.2, 2019 , pp. 1-7 More about this Journal

Abstract

This paper presents CTP (Compact Translation Page), a compact representation of translation pages, for page mapping-based flash translation layers to improve RAM utilization and reduce the response time of solid state drives. CTP can store translation information twice in a translation page and the total number of translation pages stored in flash is reduced to half. Therefore, CTP halves the RAM size of the directory of translation pages and uses the saved RAM space for translation cache. CTP shows the best response time when compared to existing page mapping-based flash translation layers.

Keywords

Flash translation layer; Solid state drive; Page mapping; NAND flash memory;

Citations & Related Records

Times Cited By KSCI : 1 (Citation Analysis)

Reference
Cited By KSCI

1	S. Lee, D. Park, T. Chung, D. Lee, S. Park, H. Song, "A log buffer based flash translation layer using fully associative sector translation," ACM Trans. Embedded Computing Sys. Vol. 6, No. 3, pp. 1-27, 2007. DOI
2	Samsung 1G x 8 bit - 2G x 8 bit- 4G x 8 bit NAND flash memory datasheet (K9XXG08UXA), https://www.scribd.com/document/ 7010323/Samsung-1G-x-8-Bit-2G-x-8-Bit-4G-x-8-Bit-NAND-Flash-Memory-Datasheet
3	J. Kim, J. M. Kim, S. H. Hoh, S. L. Min, and Y. Cho, "A Space Efficient flash translation layer for CompactFlash system," IEEE Trans. Consum. Electron., vol. 48, no. 2, pp. 366-375, May 2002. DOI
4	S.-W. Lee, D.-J. Park, et al., "A log buffer-based flash translation layer using fully-associative sector translation," ACM Trans. Emb. Comput. Syst., vol. 6, no. 3, pp. 1-27, Jul. 2007. DOI
5	J.-U. Kang, H. Jo, J.-S. Kim, and J. Lee, "A superblock-based flash translation layer for NAND flash memory," in Proc. 6th ACM IEEE Int. Conf. Embedded Softw., pp. 161-170, Oct. 2006
6	Y. Guan, et. al., "A Block-Level Log-Block Management Scheme for MLC NAND Flash Memory Storage Systems," IEEE Trans. on Computers, vol. 66, no. 9, pp. 1464-1477, Sep. 2017. DOI
7	A. Gupta, Y. Kim, and B. Urgaonkar, "DFTL: A flash translation layer employing demand-based selective caching of page-level address mappings," in Proc. 14th Int. Conf. Archit. Support Program. Languages Operating Syst., pp. 229-240, 2009.
8	H.-P. Choi, Y.-S. Kim, "An Efficient Cache Management Scheme of Flash Translation Layer for Large Size Flash Memory Drives," Journal of The Korea Society of Computer and Information Vol. 20 No. 11, pp. 31-38, November 2015 DOI
9	Storage Traces of UMass Trace Repository, http://traces.cs.umass.edu/index.php/Storage/Storage
10	D. Park, B. Debnath, and D. Du, "CFTL: An Adaptive Hybrid Flash Translation Layer with Efficient Caching Strategies," IEEE Trans. on Computers, pp. 1-15, Sep. 2011.