한국정보통신학회논문지 (Journal of the Korea Institute of Information and Communication Engineering)

  • 제23권12호
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  • Pages.1734-1737
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  • 2019
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  • 2234-4772(pISSN)
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  • 2288-4165(eISSN)
한국정보통신학회 (The Korea Institute of Information and Commucation Engineering)
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슈퍼스칼라 프로세서를 위한 고성능 하이브리드 동적 분기 예측

Hybrid Dynamic Branch Prediction to Reduce Destructive Aliasing

  • 투고 : 2019.11.25
  • 심사 : 2019.11.29
  • 발행 : 2019.12.31
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초록

This paper presents a prediction structure with a Hybrid Dynamic Branch Prediction (HDBP) scheme which decreases the number of stalls. In the application, a branch history register is dynamically adjusted to produce more unique index values of pattern history table (PHT). The number of stalls is also reduced by using the modified gshare predictor with a long history register folding scheme. The aliasing rate decreased to 44.1% and the miss prediction rate decreased to 19.06% on average compared with the gshare branch predictor, one of the most popular two-level branch predictors. Moreover, Compared with the gshare, an average improvement of 1.28% instructions per cycle (IPC) was achieved. Thus, with regard to the accuracy of branch prediction, the HDBP is remarkably useful in boosting the overall performance of the superscalar processor.

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참고문헌

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