한국전자파학회논문지 (The Journal of Korean Institute of Electromagnetic Engineering and Science)

  • 제29권5호
  • /
  • Pages.397-400
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  • 2018
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  • 1226-3133(pISSN)
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  • 2288-226X(eISSN)
한국전자파학회 (The Korean Institute of Electromagnetic Engineering and Science)
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65 nm CMOS 공정을 이용한 저면적 30~46 GHz 광대역 증폭기

30~46 GHz Wideband Amplifier Using 65 nm CMOS

  • 신미애 (성균관대학교 전자전기컴퓨터공학부) ;
  • 서문교 (성균관대학교 전자전기컴퓨터공학부)
  • Shin, Miae (Department of Electronic and Computer Engineering, Sungkyunkwan University) ;
  • Seo, Munkyo (Department of Electronic and Computer Engineering, Sungkyunkwan University)
  • 투고 : 2018.04.03
  • 심사 : 2018.05.03
  • 발행 : 2018.05.31
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초록

본 논문에서는 칩 면적을 최소화한 65 nm CMOS 기반 30~46 GHz 대역 광대역 증폭기 회로의 설계 및 측정결과에 대하여 기술하였다. 전체 증폭기의 칩 면적을 줄이기 위해 결합 인덕터를 이용한 임피던스 정합회로를 사용하였다. 제작된 광대역 증폭기 회로는 9.3 dB 최대 이득, 16 GHz의 3 dB 대역폭 및 42 % 비대역폭 등의 측정 결과를 보였다. 입출력 반사 손실은 각각 35.8~46.0 GHz 대역과 28.6~37.8 GHz 대역에서 10 dB 이상이다. 공급 전압은 1.2 V이며, 소비 전력은 42 mW이다. 3 dB 대역폭 내에서의 군 지연 변화는 19.1 ps이며, 패드를 제외한 칩 면적은 $0.09mm^2$이다.

This paper presents a miniaturized 65 nm CMOS 30~46 GHz wideband amplifier. To minimize the chip area, coupled inductors are used in the matching networks. The measurement shows that the fabricated amplifier exhibits 9.3 dB of peak gain, 16 GHz of 3 dB bandwidth, and 42 % fractional bandwidth. The measured input and output return losses were more than 10 dB at 35.8~46.0 GHz and 28.6~37.8 GHz, respectively. The chip consumes 42 mW at 1.2 V. The measured group delay variation is 19.1 ps within the 3 dB bandwidth and the chip size excluding the pads is $0.09mm^2$.

키워드

참고문헌

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