• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.11
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• pp.1247-1263
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• 1992

VHDL, which is the IEEE standard HDL, has gradually become popular in the area of hardware design, the VHDL Environment developed in this study consists of VHDL Support Environment and VHDL Using Environment. The VHDL Support Environment is composed of Analyzer, CDFG Generator for synthesis, Synthesizer, and VHDL Generator converting CDFG to VHDL. The VHDL Using Environment provides users with more convenient access to the VHDL Support Environment. The VHDL Using Environment allows accessing the tools in the VHDL Support Environment through Graphical User Interface. VHDL program can be automaticaly generated from schematics in the VHDL Using Environment.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.12
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• pp.2834-2851
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• 1997

In this paper, a design and implementation of VHDL compiler front-end, aims at supporting the full-set of VHDL '87 & '93 LRM and carring out the preprocessing of VHDL-to-C, is described. The VHDL compiler front-end includes 1)the symbol tree of analyzed data to represent the hierarchy, the scope and visibility, the overloading and homograph, the concurrent multiple stacks in VHDL, 2)the data structure and supportig routies to deal with the objects, the type and subtype, the attribute and operation in VHDL, 3)the analysis of the concurrent/sequential statements, the behavior/structural descriptions, of semantic token and the propagation of symbol & type to improve the registration and retrieval procedure of analyzed data. In the experiments with Validation Suite, the VHDL compiler front-end could support the full-set specification of VHDL LRM '87 & '93; and in the experiments to asses the performance of symantic token for the VHDL hierachy/visibility/concurrency/semantic checking, the improvement of about 20-30% could be achieved.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.12
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• pp.1-12
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• 1998

In this paper, a design and implementation of VHDL-to-C mapping in the VHDL compiler back-end is described. The analyzed data in an intermediate format(IF), produced by the compiler front-end, is transformed into a C-code model of VHDL semantics by the VHDL-to-C mapper. The C-code model for VHDL semantics is based on a functional template, including declaration, elaboration, initialization and execution parts. The mapping is carried out by utilizing C mapping templates of 129 types classified by mapping units and functional semantics, and iterative algorithms, which are combined with terminal information, to produce C codes. In order to generate the C program, the C codes are output to the functional template either directly or by combining the higher mapping result with intermediate mapping codes in the data queue. In experiments, it is shown that the VHDL-to-C mapper could completely deal with the VHDL analyzed programs from the compiler front-end, which deal with about 96% of major VHDL syntactic programs in the Validation Suite. As for the performance, it is found that the code size of VHDL-to-C is less than that of interpreter and worse than direct code compiler of which generated code is increased more rapidly with the size of VHDL design, and that the VHDL-to-C timing overhead is needed to be improved by the optimized implementation of mapping mechanism.

• The Transactions of the Korea Information Processing Society
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• v.6 no.7
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• pp.1919-1928
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• 1999

There are no standard language for the specification of speed-independent circuits because existing specification methods are designed appropriately to each synthesis methodology. This paper suggests a method of using VHDL, a standard hardware description language, for the specification and synthesis of speed-independent circuits. Because VHDL is a multi-purpose language, we define a subset of VHDL which can be used for the synthesis. We transform the VHDL description into a signal transition graph and then synthesize speed-independent circuits by using a previous synthesis algorithm which uses a signal transition graph as the specification method. We suggest a systematic transformation method which transforms each VHDL statement into a partial signal transition graph and then merges them into a signal transition graph. This work is a step towards to the development of an integrated framework in which we can utilizes the existing CAD tools based on VHDL. Also, this work will enable a easier migration of the current circuit designers into asynchronous circuit design.

• Journal of the Korea Society for Simulation
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• v.11 no.2
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• pp.55-66
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• 2002

VHDL has been. widely used in modeling and simulation of hardware designs. However, complex relationship between components of the designs makes the VHDL modeling problem very difficult. Furthermore, after the initial creation of VHDL models, they evolve into many versions over their lifetime. To cope with such difficulties, this paper proposes a new methodology for the management of VHDL models supporting versions. Its conceptual bases are system entity structure and relational database. Within the methodology, a family of hierarchical structures of a design is organized in the form of VHDL model structure. It is, in turn, represented in the form of relational tables. Once the model structure is built in such a way, a specific simulation model which meets design objective is pruned from the model structure. The details of VHDL codes are systematically synthesized by combining it with the primitive models in a model base. These algorithms are also defined in terms of relational algebraic operations.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1015-1018
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• 2003

As increasing the size and complexity of hard-ware and software system, more efficient design methodology has been developed. Especially design-reuse technique enables fast system development via integrating existing hardware and software. For this technique available hardware/software should be prepared as component-based parts, adaptable to various systems. This paper introduces a component-based VHDL analyzer allowing to be embedded in other applications, such as simulator, synthesis tool, or smart editor. VHDL analyzer parses VHDL description input, and performs lexical, syntactic, semantic checking, and finally generates intermediate-form data as the result. VHDL has full-features of object-oriented language such as data abstraction, inheritance, and polymorphism. To support these features special analysis algorithm and intermediate form is required. This paper summarizes practical issues on implementing high-performance/quality VHDL analyzer and provides its solution that is based on the intensive experience of VHDL analyzer development.

• Proceedings of the Korean Information Science Society Conference
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• 1999.10c
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• pp.54-56
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• 1999

현재 많은 내장형 시스템을 구현하기 위한 방법론으로 가상 프로토타입(VP)을 이용하고 있다. 본 논문에서는 가상 프로토타입을 이용하여 내장형 시스템의 설계 및 구현을 위해 사용되는 시스템 명세 언어인 SpecCharts로 명세된 시스템을 동기적 의미론에 만족하는 SpecCharts의 Subset을 규명하여 동기화 형태로 해당명세를 변환시키고 이로부터 synchronous VHDL 코드로 생성할 수 있는 방법을 설계하였다. 동기적 의미론을 만족시키기 위하여 비결정적인 추상적인 모델(NDAM)을 이용하여 SpecCharts로부터 VHDL ？로 변환하는 방법을 제시하고, 변환된 VHDL 코드를 동기적 VHDL 코드로 변환하기 위하여 W. Baker에 의해 규명된 동기적 VHDL subset 적용하여 synchronous VHDL 코드를 생성하는 방법을 제안한다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.12
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• pp.1256-1263
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• 2003

In this paper, we analyzed the channel coding scheme of DVB and ISDB standard for high-speed satellite broadcasting. Also, this paper proposed optimal parameters of decoder with variable coding rate for implementation. According to the optimal parameters, the pragmatic TCM of rate 213, 5/6, 819 was modeled by VHDL. The results designed by VHDL can be verified.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.1
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• pp.96-102
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• 1995

This paper presents the VHSIC Hardware Description Language(VHDL) implementation of the Fixed Point Covariance Lattice(FLAT) algorithm for an Linear Predictive Coding(LPC) analysis and its related algorithms, such as the forth order high pass Infinite Impulse Response(IIR) filter, covariance matrix calculation, and Spectral Smoothing Technique(SST) in the Vector Sum Exited Linear Predictive(VSELP) speech coder that has been Selected as the standard speech coder for the North America and Japanese digital cellular. Existing Digital Signal Processor(DSP) chips used in digital cellular phones are derived from general purpose DSP chips, and thus, these DSP chips may not be optimal and effective architectures are to be designed for the above mentioned algorithms. Then we implemented the VHDL code based on the C code, Finally, we verified that VHDL results are the same as C code results for real speech data. The implemented VHDL code can be used for performing logic synthesis and for designing an LPC Application Specific Integrated Circuit(ASOC) chip and DsP chips. We first developed the C language code to investigate the correctness of algorithms and to compare C code results with VHDL code results block by block.

• ETRI Journal
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• v.11 no.1
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• pp.97-108
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• 1989

본 논문은 VHDL(Very High Speed IC Hardware Description Language)로 기술(description)한 입력을 받아 구문의 정확성을 검사하기 위한 구문 분석기 개발에 관한 것이다. 본 연구에서 채택한 VHDL 버젼은 1987년 12월 미국의 IEEE에서 표준 하드웨어 기술 언어로 공표한 VHDL 1076버젼을 대상으로 하고 있다. 현재는 입력이 구문과 일치하는가를 검사하여 맞지 않는 경우 에러 메시지(error message)를 내보내며, 맞는 경우 구문이 정확히 기술되었음을 사용자에게 통보한다. VHDL 구문 분석기는 향후 본 연구실에서 개발한 VHDL 시뮬레이터 및 합성기에서 front-end 툴로써 이용할 계획이며, VHDL 구문에 의한 기술을 통해 언어의 이해에도 이용할 수 있다. 프로그램은 SUN-3/160C 컴퓨터의 UNIX 4.2 BSD하에서 lex, yacc를 이용하여, C언어로 구현되었다.