Journal of Power Electronics

  • 제18권2호
  • /
  • Pages.356-363
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  • 2018
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  • 1598-2092(pISSN)
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  • 2093-4718(eISSN)
전력전자학회 (The Korean Institute of Power Electronics)
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A Forward-Integrated Buck DC-DC Converter with Low Voltage Stress for High Step-Down Applications

  • 투고 : 2017.04.21
  • 심사 : 2017.10.18
  • 발행 : 2018.03.20
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⟨ 이전 논문 다음 논문 ⟩

초록

The combination of a buck converter and a forward converter can be considered to accomplish a high step-down non-isolated converter. To decrease the insufficient step-down ratio of a regular buck converter and to distribute switch voltage stress, a forward-integrated buck (FIB) converter is proposed in this paper. The proposed interleaved DC-DC converter provides an additional step-down gain with the help of a forward converter. In addition to its simple structure, the transformer flux reset problem is solved and an additional magnetic core reset winding is not required. The operational principle and an analysis of the proposed FIB converter are presented and verified by experimental results obtained with a 240 W, 150 V/24 V prototype.

키워드

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Fig. 1. Buck converter with a series input dc voltage.

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Fig. 2. Proposed forward integrated buck (FIB) converter.

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Fig. 3. Key waveforms of the proposed converter.

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Fig. 4. Equivalent circuit for each of the operating intervals.

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Fig. 5. Voltage conversion ratio versus the duty cycle of theproposed converter with n=1 for a regular buck converter, aregular forward converter (n=1) and the buck converter with atapped inductor (n = 1).

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Fig. 6. Voltage conversion ratio versus the duty cycle of theproposed converter under different turn ratios.

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Fig. 7. PWM control scheme of the proposed converter.

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Fig. 8. Photo of the power section of the prototype

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Fig. 9. Voltage and current waveforms of: (a) S1 (time scale1μS/div), (b) S1 (time scale 250nS/div), (c) D1, (d) D3, (e) D4.

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Fig. 10. Voltage and current waveforms of: (a) S2, (b) D2.

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Fig. 11. Efficiency comparison between the proposed converterand a conventional interleaved buck converter.

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Fig. 12. Dynamic response of the proposed converter (n=1).

TABLE I COMPARISON BETWEEN THE PROPOSED CONVERTER AND THREE OTHER CONVERTERS

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TABLE II SEMICONDUCTOR CURRENT STRESS ANALYSIS

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TABLE III PARAMETERS OF THE IMPLEMENTED PROTOTYPE

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TABLE IV IMPORTANT LOSSES IN THE PROPOSED CONVERTER

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