Fig. 1. Schematic of the APS.
Fig. 2. Operating principle of binary processing.
Fig. 3. Schematic of (a) the two-stage comparator and (b) the dynamic comparator.
Fig. 4. Schematic of double sampling.
Fig. 5. Timing diagram of the proposed CMOS binary image sensor.
Fig. 6. Block diagram of the proposed CMOS image sensor.
Fig. 7. Schematic of a unit column readout circuits.
Fig. 8. Layout of column parallel readout circuits.
Fig. 9. Simulation results for output current according to the type of comparator.
Fig. 10. Histogram of Monte Carlo simulation.
Table 1. Comparison of two comparators.
Table 2. Results of Monte Carlo simulation before and after double sampling.
Table 3. Characteristics of the proposed CMOS binary image sensor.
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