Journal of Sensor Science and Technology (센서학회지)

The Korean Sensors Society (한국센서학회)
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CMOS Binary Image Sensor with Gate/Body-Tied PMOSFET-Type Photodetector for Low-Power and Low-Noise Operation

  • Lee, Junwoo (School of Electrical Engineering, Kyungpook National Unversity) ;
  • Choi, Byoung-Soo (School of Electrical Engineering, Kyungpook National Unversity) ;
  • Seong, Donghyun (School of Electrical Engineering, Kyungpook National Unversity) ;
  • Lee, Jewon (School of Electrical Engineering, Kyungpook National Unversity) ;
  • Kim, Sang-Hwan (School of Electrical Engineering, Kyungpook National Unversity) ;
  • Lee, Jimin (School of Electrical Engineering, Kyungpook National Unversity) ;
  • Shin, Jang-Kyoo (School of Electrical Engineering, Kyungpook National Unversity) ;
  • Choi, Pyung (School of Electrical Engineering, Kyungpook National Unversity)
  • Received : 2018.09.12
  • Accepted : 2018.11.21
  • Published : 2018.11.30
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Abstract

A complementary metal oxide semiconductor (CMOS) binary image sensor is proposed for low-power and low-noise operation. The proposed binary image sensor has the advantages of reduced power consumption and fixed pattern noise (FPN). A gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector is used as the proposed CMOS binary image sensor. The GBT PMOSFET-type photodetector has a floating gate that amplifies the photocurrent generated by incident light. Therefore, the sensitivity of the GBT PMOSFET-type photodetector is higher than that of other photodetectors. The proposed CMOS binary image sensor consists of a pixel array with $394(H){\times}250(V)$ pixels, scanners, bias circuits, and column parallel readout circuits for binary image processing. The proposed CMOS binary image sensor was analyzed by simulation. Using the dynamic comparator, a power consumption reduction of approximately 99.7% was achieved, and this performance was verified by the simulation by comparing the results with those of a two-stage comparator. Also, it was confirmed using simulation that the FPN of the proposed CMOS binary image sensor was successfully reduced by use of the double sampling process.

Keywords

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Fig. 1. Schematic of the APS.

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Fig. 2. Operating principle of binary processing.

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Fig. 3. Schematic of (a) the two-stage comparator and (b) the dynamic comparator.

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Fig. 4. Schematic of double sampling.

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Fig. 5. Timing diagram of the proposed CMOS binary image sensor.

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Fig. 6. Block diagram of the proposed CMOS image sensor.

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Fig. 7. Schematic of a unit column readout circuits.

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Fig. 8. Layout of column parallel readout circuits.

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Fig. 9. Simulation results for output current according to the type of comparator.

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Fig. 10. Histogram of Monte Carlo simulation.

Table 1. Comparison of two comparators.

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Table 2. Results of Monte Carlo simulation before and after double sampling.

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Table 3. Characteristics of the proposed CMOS binary image sensor.

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