Journal of Sensor Science and Technology (센서학회지)

The Korean Sensors Society (한국센서학회)
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Averaging Current Adjustment Technique for Reducing Pixel Resistance Variation in a Bolometer-Type Uncooled Infrared Image Sensor

  • Kim, Sang-Hwan (School of Electronics Engineering, Kyungpook National Unversity) ;
  • Choi, Byoung-Soo (School of Electronics Engineering, Kyungpook National Unversity) ;
  • Lee, Jimin (School of Electronics Engineering, Kyungpook National Unversity) ;
  • Lee, Junwoo (School of Electronics Engineering, Kyungpook National Unversity) ;
  • Park, Jae-Hyoun (Korea Electronics Technology Institute) ;
  • Lee, Kyoung-Il (Korea Electronics Technology Institute) ;
  • Shin, Jang-Kyoo (School of Electronics Engineering, Kyungpook National Unversity)
  • Received : 2018.09.10
  • Accepted : 2018.11.21
  • Published : 2018.11.30
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Abstract

This paper presents an averaging current adjustment technique for reducing the pixel resistance variation in a bolometer-type uncooled infrared image sensor. Each unit pixel was composed of an active pixel, a reference pixel for the averaging current adjustment technique, and a calibration circuit. The reference pixel was integrated with a polysilicon resistor using a standard complementary metal-oxide-semiconductor (CMOS) process, and the active pixel was applied from outside of the chip. The averaging current adjustment technique was designed by using the reference pixel. The entire circuit was implemented on a chip that was composed of a reference pixel array for the averaging current adjustment technique, a calibration circuit, and readout circuits. The proposed reference pixel array for the averaging current adjustment technique, calibration circuit, and readout circuit were designed and fabricated by a $0.35-{\mu}m$ standard CMOS process.

Keywords

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Fig. 1. Circuit diagram of unit pixel.

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Fig. 2. Block diagram of averaging current adjustment technique using reference pixel array.

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Fig. 3. Layout of designed readout circuit.

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Fig. 4. (a) Block diagram of entire chip and (b) timing diagram of entire chip.

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Fig. 6. Measurement result of pixel output voltage through integrator: (a) before calibration and (b) after calibration.

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Fig. 5. Simulation result of pixel output voltage through integrator: (a) before calibration and (b) after calibration.

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Fig. 7. (a) Fabricated chip and (b) test board.

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