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Electronics and Telecommunications Research Institute (한국전자통신연구원)
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Acceleration of Simulated Fault Injection Using a Checkpoint Forwarding Technique

  • Na, Jongwhoa (Department of Electronics, Korea Aerospace University) ;
  • Lee, Dongwoo (Avionics Research Institute of Korea Aerospace University)
  • Received : 2016.03.04
  • Accepted : 2017.04.24
  • Published : 2017.08.01
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Abstract

Simulated fault injection (SFI) is widely used to assess the effectiveness of fault tolerance mechanisms in safety-critical embedded systems (SCESs) because of its advantages such as controllability and observability. However, the long test time of SFI due to the large number of test cases and the complex simulation models of modern SCESs has been identified as a limiting factor. We present a method that can accelerate an SFI tool using a checkpoint forwarding (CF) technique. To evaluate the performance of CF-based SFI (CF-SFI), we have developed a CF mechanism using Verilog fault-injection tools and two systems under test (SUT): a single-core-based co-simulation model and a triple modular redundant co-simulation model. Both systems use the Verilog simulation model of the OpenRISC 1200 processor and can execute the embedded benchmarks from MiBench. We investigate the effectiveness of the CF mechanism and evaluate the two SUTs by measuring the test time as well as the failure rates. Compared to the SFI with no CF mechanism, the proposed CF-SFI approach reduces the test time of the two SUTs by 29%-45%.

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References

  1. D.W. King et al., "UAV Failure Rate Criteria for Equivalent Level of Safety," Int. Helicopter Safety Symp., Montreal, Canada, Sept. 26-29, 2005, pp. 1-9.
  2. R. Schaefer, "Unmanned Aerial Vehicle Reliability Study," Office of the Secretary of Defense, Washington, D.C., USA, 2003.
  3. M.L. Shooman, "Bohr Bugs, Mandel Bugs, Exhaustive Testing and Unintended Automobile Acceleration," Int. Conf. Soft. Rel. Eng., Dallas, TX, USA, Nov. 27-30, 2012, pp. 5-6.
  4. H. Alemzadeh et al., "Systems-Theoretic Safety Assessment of Robotic Telesurgical Systems," Int. Conf. SAFECOMP 2015, Delft, Netherlands, Sept. 23-25, 2015, pp. 213-227.
  5. K. Potiron et al., From Fault Classification to Fault Tolerance for Multi-agent Systems, London, UK: Springer, 2013.
  6. S. Borkar, "Designing Reliable Systems from Unreliable Components: the Challenges of Transistor Variability and Degradation," IEEE Micro, vol. 25, no. 6, Nov. 2005, pp. 10-16. https://doi.org/10.1109/MM.2005.110
  7. S. Mukherjee, Architecture Design for Soft Errors, San Francisco, CA, USA: Morgan Kaufmann, 2011.
  8. R. Velazco et al., Radiation Effects on Embedded Systems, Netherland: Springer Science & Business Media, 2007.
  9. I. Koren et al., Fault-Tolerant Systems, San Francisco, CA, USA: Morgan Kaufmann, 2010.
  10. D.J. Sorin, Fault Tolerant Computer Architecture, San Rafael, CA, USA: Morgan and Claypool, 2009, pp. 1- 104.
  11. A. Moniruzzaman et al., "Comparative Study on Agile Software Development Methodologies," Global J. Comput. Sci. Technol., vol. 13, no. 7, July 2013, pp. 5-18.
  12. C. Ebert et al., "Embedded Software: Facts, Figures, and Future," Comput., vol. 42, no. 4, Apr. 2009, pp. 42-52. https://doi.org/10.1109/MC.2009.118
  13. A. Benso et al., Fault Injection Techniques and Tools for Embedded Systems Reliability Evaluation, NY, USA: Springer Science & Business Media, 2003.
  14. M. Kooli et al., "A Survey on Simulation-Based Fault Injection Tools for Complex Systems," Int. Conf. Des. Technol. Integr. Syst., Santorini, Greece, May 6-8, 2014, pp. 1-6.
  15. H. Ziade, R. Ayoubi, and R. Velazco, "A Survey on Fault Injection Techniques," Int. Arab J. Inform. Technol., vol. 1, no. 2, July 2004, pp. 171-186.
  16. P. Maistri and R. Leveugle, "Towards Automated Fault Pruning with Petri Nets," On-line Testing Symp., Lisbon, Portugal, June 24-26, 2009, pp. 41-46.
  17. M. Maniatakos et al., "AVF Analysis Acceleration via Hierarchical Fault Pruning," Eur. Test Symp., Trondheim, Norway, May 23-27, 2011, pp. 87-92.
  18. H. Schirmeier, C. Brochert, and O. Spinczyk, "Rapid Fault- Space Exploration by Evolutionary Pruning," Int. Conf. SAFECOMP 2014, Florence, Italy, Sept. 8-12, 2014, pp. 17-32.
  19. M.R. Guthaus et al., "MiBench: A Free, Commercially Representative Embedded Benchmark Suite," IEEE Int. Workshop Workload Characterization, Austin, TX, USA, Dec. 2, 2001, pp. 3-14.
  20. D. Lee and J. Na, "A Novel Simulation Fault Injection Method for Dependability Analysis," IEEE Des. Test Comput., vol. 26, no. 6, Nov. 2009, pp. 50-60. https://doi.org/10.1109/MDT.2009.135
  21. J. Na and D. Lee, "Simulated Fault Injection using Simulator Modification Technique," ETRI J., vol. 33, no. 1, Feb. 2011, pp. 50-59. https://doi.org/10.4218/etrij.11.0110.0106
  22. C. Dawson, S.K. Pattanam, and D. Roberts, "The Verilog Procedural Interface for the Verilog Hardware Description Language," IEEE Int. Verilog HDL Conf., Santa Clara, CA, USA, Feb. 1996, pp. 17-23.
  23. D. Mattsson and M. Christensson, "Evaluation of Synthesizable CPU Cores," M.S. thesis, Dept. Comput. Eng., Chalmers Univ., Sweden, 2004.
  24. C. Constantinescu, M. Butler, and C. Weller, "Error Injection-Based Study of Soft Error Propagation in AMD Bulldozer Microprocessor Module," IEEE/IFIP Int. Conf. Dependable Syst. Netw., Boston, MA, USA, June 25-28, 2012, pp. 1-6.
  25. D.T. Smith et al., "A Method to Determine Equivalent Fault Classes for Permanent and Transient Faults," Rel. Maintainability Symp., Washington, D.C., USA, Jan. 16-19, 1995, pp. 418-424.
  26. A. Benso et al., "Fault-List Collapsing for Fault-Injection Experiments," Rel. Maintainability, Symp., Anaheim, CA, USA, Jan. 19-22, 1998, pp. 383-388.
  27. L. Berrojo et al., "New Techniques for Speeding-up Fault-Injection Campaigns," Des. Autom. Test Europe Conf. Exhibition, Paris, France, Mar. 4-8, 2002, pp. 847- 852.
  28. R. Barbosa et al., "Assembly-Level Pre-injection Analysis for Improving Fault Injection Efficiency," Int. Conf. Eur. Dependable Comput., Budapest, Hungary, Apr. 20-22, 2005, pp. 246-262.
  29. J. Grinschgl et al., "Efficient Fault Emulation based on Post-injection Fault Effect Analysis (PIFEA)," Int. Midwest Sypm. Conf. Circuits Syst., Boise, ID, USA, Aug. 5-8, 2012, pp. 526-529.
  30. S.K.S. Hari et al., "Relyzer: Application Resiliency Analyzer for Transient Faults," IEEE Micro, vol. 33, no. 3, May 2013, pp. 58-66. https://doi.org/10.1109/MM.2013.30
  31. B. Dobel et al., "Investigating the Limitations of PVF for Realistic Program Vulnerability Assessment," Int. Conf. HiPEAC Workshop Des. Rel., Berlin, Germany, Jan. 21-23, 2013.
  32. J. Li and Q. Tan, "SmartInjector: Exploiting Intelligent Fault Injection for SDC Rate Analysis," IEEE Int. Symp. Defect Fault Tolerance VLSI Nanotechnol. Syst., New York, USA, Oct. 2-4, 2013, pp. 236-242.
  33. C. Hesscot et al., "A Methodology for Stochastic Fault Simulation in VLSI Processor Architectures," Semiconductor Research Corporation, June 2010.
  34. C. Artho et al., "Using Checkpointing and Virtualization for Fault Injection," Int. Symp. Comput. Netw., Shizuoka, Japan, Dec. 10-12, 2015, pp. 347-372.
  35. H. Schirmeier, L. Rademacher, and O. Spinczyk, "Smart- Hopping: Highly Efficient ISA-Level Fault Injection on Real Hardware," IEEE Eur. Test Sym., Paderborn, Germany, May 26-30, 2014, pp. 1-6.
  36. K. Parasyris et al., "GemFI: A Fault Injection Tool for Studying the Behavior of Applications on Unreliable Substrates," Int. Conf. Dependable Syst. Netw., Atlanta, GA, USA, June 23-26, 2014, pp. 622-629.