Transactions on Electrical and Electronic Materials

  • 제18권5호
  • /
  • Pages.257-260
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  • 2017
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  • 1229-7607(pISSN)
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  • 2092-7592(eISSN)
한국전기전자재료학회 (The Korean Institute of Electrical and Electronic Material Engineers)
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Low Dropout Voltage Regulator Using 130 nm CMOS Technology

  • Marufuzzaman, Mohammad (Department of Electrical, Electronic and Systems Engineering, Faculty of Engineering and Built Environment, Universiti Kebangsaan Malaysia) ;
  • Reaz, Mamun Bin Ibne (Department of Electrical, Electronic and Systems Engineering, Faculty of Engineering and Built Environment, Universiti Kebangsaan Malaysia) ;
  • Rahman, Labonnah Farzana (Department of Electrical, Electronic and Systems Engineering, Faculty of Engineering and Built Environment, Universiti Kebangsaan Malaysia) ;
  • Mustafa, Norhaida Binti (Department of Electrical, Electronic and Systems Engineering, Faculty of Engineering and Built Environment, Universiti Kebangsaan Malaysia) ;
  • Farayez, Araf (Department of Electrical, Electronic and Systems Engineering, Faculty of Engineering and Built Environment, Universiti Kebangsaan Malaysia)
  • 투고 : 2016.11.09
  • 심사 : 2017.03.23
  • 발행 : 2017.10.25
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초록

In this paper, we present the design of a 4.5 V low dropout (LDO) voltage regulator implemented in the 130 nm CMOS process. The design uses a two-stage cascaded operational transconductance amplifier (OTA) as an error amplifier, with a body bias technique for reducing dropout voltages. PMOS is used as a pass transistor to ensure stable output voltages. The results show that the proposed LDO regulator has a dropout voltage of 32.06 mV when implemented in the130 nm CMOS process. The power dissipation is only 1.3593 mW and the proposed circuit operates under an input voltage of 5V with an active area of $703{\mu}m^2$, ensuring that the proposed circuit is suitable for low-power applications.

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참고문헌

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