DOI QR코드

DOI QR Code

Design and Implementation of a Sequential Polynomial Basis Multiplier over GF(2m)

  • Mathe, Sudha Ellison (Department of Electronics and Communication Engineering, National Institute of Technology-Warangal) ;
  • Boppana, Lakshmi (Department of Electronics and Communication Engineering, National Institute of Technology-Warangal)
  • Received : 2016.08.29
  • Accepted : 2017.02.22
  • Published : 2017.05.31

Abstract

Finite field arithmetic over GF($2^m$) is used in a variety of applications such as cryptography, coding theory, computer algebra. It is mainly used in various cryptographic algorithms such as the Elliptic Curve Cryptography (ECC), Advanced Encryption Standard (AES), Twofish etc. The multiplication in a finite field is considered as highly complex and resource consuming operation in such applications. Many algorithms and architectures are proposed in the literature to obtain efficient multiplication operation in both hardware and software. In this paper, a modified serial multiplication algorithm with interleaved modular reduction is proposed, which allows for an efficient realization of a sequential polynomial basis multiplier. The proposed sequential multiplier supports multiplication of any two arbitrary finite field elements over GF($2^m$) for generic irreducible polynomials, therefore made versatile. Estimation of area and time complexities of the proposed sequential multiplier is performed and comparison with existing sequential multipliers is presented. The proposed sequential multiplier achieves 50% reduction in area-delay product over the best of existing sequential multipliers for m = 163, indicating an efficient design in terms of both area and delay. The Application Specific Integrated Circuit (ASIC) and the Field Programmable Gate Array (FPGA) implementation results indicate a significantly less power-delay and area-delay products of the proposed sequential multiplier over existing multipliers.

Keywords

References

  1. B. Schneier, "Foundations," in Proc. of Applied Cryptography, 2nd ed., John Wiley & Sons Inc., U.K., pp. 1-4, 1996.
  2. "FIPS PUB 46-3 Data Encryption Standard (DES)," NIST - Federal Information Processing Standard Publication, October, 1999.
  3. "FIPS PUB 197 Advanced Encryption Standard (AES)," NIST - Federal Information Processing Standard Publication, November, 2001.
  4. N. Koblitz, "Elliptic curve cryptosystems," Mathematics of computation, vol. 48, no. 177, pp. 203-209, January, 1987. https://doi.org/10.1090/S0025-5718-1987-0866109-5
  5. V. Miller, "Use of elliptic curves in cryptography," in Proc. of Advances in Cryptology-Crypto'85, pp. 417-426, August 18-22, 1986.
  6. R.L. Rivest, A. Shamir, and L. Adleman, "A method for obtaining digital signatures and public-key cryptosystems," Communications of the ACM, vol. 21, no. 2, pp. 120-126, February, 1978. https://doi.org/10.1145/359340.359342
  7. T.C. Chen, S.W. Wei, and H.J. Tsai, "Arithmetic unit for finite field GF($2^m$)," IEEE Transactions on Circuits and Systems I, vol. 55, no. 3, pp. 828-837, May, 2008. https://doi.org/10.1109/TCSI.2008.919757
  8. K. Kobayashi, and N. Takagi, "A combined circuit for multiplication and inversion in GF($2^m$)," IEEE Transactions on Circuits and Systems II, vol. 55, no. 11, pp. 1144-1148, December, 2008. https://doi.org/10.1109/TCSII.2008.2003347
  9. K. Kobayashi, and N. Takagi, "Fast hardware algorithm for division in GF($2^m$) based on the extended euclid's algorithm with parallelization of modular reductions," IEEE Transactions on Circuits and Systems II, vol. 56, no. 8, pp. 644-648, July, 2009. https://doi.org/10.1109/TCSII.2009.2024253
  10. R. Lidl, and H. Niederreiter, "Introduction to finite fields and their applications," Revised edition, Cambridge University Press, Cambridge, 1994.
  11. F.J. MacWilliams, and N.J.A. Sloane, "The theory of error correcting codes," 1st ed., North-Holland Publishing Company, New York, 1977.
  12. C.C. Wang, and D. Pei, "A VLSI design for computing exponentiation in GF($2^m$) and its application to generate pseudorandom number sequences," IEEE Transactions on Computers, vol. 39, no. 2, pp. 258-262, February, 1990. https://doi.org/10.1109/12.45211
  13. E.R. Berlekamp, "Bit-serial Reed Solomon encoder," IEEE Transactions on Information Theory, vol. 28, no. 6, pp. 869-874, November, 1982. https://doi.org/10.1109/TIT.1982.1056591
  14. R. Schroeppel, H. Orman, S. OMalley, et al., "Fast key exchange with elliptic curve systems," in Proc. of Advances in Cryptology-Crypto'95, pp. 43-56, August 27-31, 1995.
  15. E.D. Win, A. Bosselaers, S. Vandenberghe, et al., "A fast software implementation for arithmetic operations in GF($2^n$)," in Proc. of Advances in Cryptology-ASIACRYPT '96, pp. 65-76, November 3-7, 1996.
  16. A.J. Menezes, Applications of finite fields, Kluwer Academic, Massachusetts, 1993.
  17. S. Roman, Field theory, 2nd ed., Springer Verlag, New York, 2006.
  18. A. Reyhani-Masoleh, and M.A. Hasan, "Low complexity bit parallel architectures for polynomial basis multiplication over GF($2^m$)," IEEE Transactions on Computers, vol. 53, no. 8, pp. 945-959, June, 2004. https://doi.org/10.1109/TC.2004.47
  19. J.L. Imana, J.M. Sanchez, and F. Tirado, "Bit-parallel finite field multipliers for irreducible trinomials," IEEE Transactions on Computers, vol. 55, no. 5, pp. 520-533, April, 2006. https://doi.org/10.1109/TC.2006.69
  20. A. Cilardo, "Fast Parallel GF ($2^m$) Polynomial Multiplication for All Degrees," IEEE Transactions on Computers, vol. 62, no. 5, pp. 929-943, May, 2013. https://doi.org/10.1109/TC.2012.63
  21. M. Nikooghadam, and A. Zakerolhosseini, "Utilization of Pipeline Technique in AOP Based Multipliers with Parallel Inputs," Journal of Signal Processing Systems, vol. 72, no. 1, pp. 57-62, July, 2013. https://doi.org/10.1007/s11265-012-0702-6
  22. A. Karatsuba, and Y. Ofman, "Multiplication of multidigit numbers on automata," Soviet physics doklady, vol. 7, pp. 595-596, January, 1963.
  23. M. Morales-Sandoval, C. Feregrino-Uribe, and P. Kitsos, "Bit-serial and digit-serial GF($2^m$) Montgomery multipliers using linear feedback shift registers," IET Computers & Digital Techniques, vol. 5, no. 2, pp. 86-94, April, 2011. https://doi.org/10.1049/iet-cdt.2010.0021
  24. E.D. Mastrovito, "VLSI Architectures for Computations in Galois Fields," PhD thesis, Linkoping University, Linkoping, Sweden, 1991.
  25. D.G. Cantor, "On arithmetical algorithms over finite fields," Journal of Combinatorial Theory, vol. 50, no. 2, pp. 285-300, March, 1989. https://doi.org/10.1016/0097-3165(89)90020-4
  26. J.V.Z. Gathen, and J. Gerhard, "Arithmetic and factorization of polynomial over $F^2$," in Proc. of International Symposium on Symbolic and algebraic computation, pp. 1-9, July 24-26, 1996.
  27. P.K. Meher, "Systolic and non-systolic scalable modular designs of finite field multipliers for reed-solomon codec," IEEE Transactions on Very Large Scale Integrated Systems, vol. 17, no. 6, pp. 747-757, March, 2009. https://doi.org/10.1109/TVLSI.2008.2006080
  28. J.L. Imana, "Low Latency GF($2^m$) Polynomial Basis Multiplier," IEEE Transactions on Circuits and Systems I, vol. 58, no. 5, pp. 935-946, May, 2011. https://doi.org/10.1109/TCSI.2010.2089553
  29. H. Ho, "Design and Implementation of a Polynomial Basis Multiplier Architecture Over GF($2^m$)," Journal of Signal Processing Systems, vol. 75, no. 3, pp. 203-208, June, 2014. https://doi.org/10.1007/s11265-013-0791-x
  30. A.P. Fournaris, and O. Koufopavlou, "Versatile multiplier architectures in GF(2k) fields using the Montgomery multiplication algorithm," INTEGRATION the VLSI journal, vol. 41, no. 3, pp. 371-384, May, 2008. https://doi.org/10.1016/j.vlsi.2007.07.004
  31. P.K. Meher, "Systolic and super-systolic multipliers for finite field based on irreducible trinomials," IEEE Transactions on Circuits and Systems I, vol. 55, no. 4, pp. 1031-1040, May, 2008. https://doi.org/10.1109/TCSI.2008.916622
  32. M.A. Hasan, and M. Ebtedaei, "Efficient architectures for computations over variable dimensional Galois fields," IEEE Transactions on Circuits and Systems I, vol. 45, no. 11, pp. 1205-1210, November, 1998.
  33. P. Kitsos, G. Theodoridis, and O. Koufopavlou, "An efficient reconfigurable multiplier architecture for Galois field GF($2^m$)," Microelectronics Journal, vol. 34, no. 10, pp. 975-980, October, 2003. https://doi.org/10.1016/S0026-2692(03)00172-1
  34. J.H. Guo, and C.L. Wang, "Digit-serial systolic multiplier for finite fields GF($2^m$)," IEE Proceedings on Computers and Digital Techniques, vol. 145, no. 2, pp. 143-148, April, 1998. https://doi.org/10.1049/ip-cdt:19981906
  35. L. Song, and K.K. Parhi, "Low-energy digit-serial/parallel finite field multipliers," The Journal of VLSI Signal Processing - Systems for Signal, Image, and Video Technology, vol. 19, no. 2, pp. 149-166, July, 1998. https://doi.org/10.1023/A:1008013818413
  36. H. Fan, and M.A. Hasan, "Fast bit parallel-shifted polynomial basis multipliers in GF($2^n$)," IEEE Transactions on Circuits and Systems I, vol. 53, no. 12, pp. 2606-2615, December, 2006. https://doi.org/10.1109/TCSI.2006.883855
  37. C.Y. Lee, "Low complexity bit-parallel systolic multiplier over GF($2^m$) using irreducible trinomials," IEE Proceedings on Computers and Digital Techniques, vol. 150, no. 1, pp. 39-42, February, 2003. https://doi.org/10.1049/ip-cdt:20030061
  38. C.Y. Lee, Y.H. Chen, C.W. Chiou, and et al., "Unified Parallel Systolic Multiplier Over GF($2^m$)," Journal of Computer Science and Technology, vol. 22, no. 1, pp. 28-38, January, 2007. https://doi.org/10.1007/s11390-007-9003-0
  39. W.C. Tsai, and S.J. Wang, "Two systolic architectures for multiplication in GF($2^m$)," IEEE Proceedings on Computers and Digital Techniques, vol. 147, no. 6, pp. 375-382, December, 2000. https://doi.org/10.1049/ip-cdt:20000785
  40. K.W. Kim, and J.C. Jeon, "Polynomial Basis Multiplier Using Cellular Systolic Architecture," IETE Journal of Research, vol. 60, no. 2, pp. 194-199, June 2014. https://doi.org/10.1080/03772063.2014.914699
  41. A. Reyhani-Masoleh, and M.A. Hasan, "A new construction of Massey-Omura parallel multiplier over GF($2^m$)," IEEE Transactions on Computers, vol. 51, no. 5, pp. 511-520, June, 2002. https://doi.org/10.1109/TC.2002.1004590
  42. H. Wu, and M.A. Hasan, "Low complexity bit-parallel multipliers for a class of finite fields," IEEE Transactions on Computers, vol. 47, no. 8, pp. 883-887, August, 1998. https://doi.org/10.1109/12.707588
  43. S.S. Erdem, T. Yanik, and C.K. Koc, "Polynomial Basis Multiplication over GF($2^m$)," in Proc. of Acta Applicandae Mathematicae, vol. 93, pp. 33-55, September, 2006. https://doi.org/10.1007/s10440-006-9047-0
  44. F. Rodriguez-Henriquez, N.A. Saqib, A.D. Perez, and et al., "Binary Finite Field Arithmetic," in Proc. of Cryptographic Algorithms on Reconfigurable Hardware, 1st ed., Springer, New York, pp. 139-188, 2007.
  45. A. Zakerolhosseini, and M. Nikooghadam, "Low-power and high-speed design of a versatile bit-serial multiplier in finite fields GF ($2^m$)," INTEGRATION, the VLSI journal, vol. 46, no. 2, pp. 211-217, March, 2013. https://doi.org/10.1016/j.vlsi.2012.03.001