IEIE Transactions on Smart Processing and Computing

The Institute of Electronics and Information Engineers (대한전자공학회)
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Efficient Parallel Block-layered Nonbinary Quasi-cyclic Low-density Parity-check Decoding on a GPU

  • Thi, Huyen Pham (Department of Information and Communication Engineering, Inha University) ;
  • Lee, Hanho (Department of Information and Communication Engineering, Inha University)
  • Received : 2017.04.06
  • Accepted : 2017.05.10
  • Published : 2017.06.30
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Abstract

This paper proposes a modified min-max algorithm (MMMA) for nonbinary quasi-cyclic low-density parity-check (NB-QC-LDPC) codes and an efficient parallel block-layered decoder architecture corresponding to the algorithm on a graphics processing unit (GPU) platform. The algorithm removes multiplications over the Galois field (GF) in the merger step to reduce decoding latency without any performance loss. The decoding implementation on a GPU for NB-QC-LDPC codes achieves improvements in both flexibility and scalability. To perform the decoding on the GPU, data and memory structures suitable for parallel computing are designed. The implementation results for NB-QC-LDPC codes over GF(32) and GF(64) demonstrate that the parallel block-layered decoding on a GPU accelerates the decoding process to provide a faster decoding runtime, and obtains a higher coding gain under a low $10^{-10}$ bit error rate and low $10^{-7}$ frame error rate, compared to existing methods.

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References

  1. R.G. Gallager, Low-density parity-check codes, Information Theory, IRE Transactions on, vol.8, no.1, pp.21-28, 1962. https://doi.org/10.1109/TIT.1962.1057683
  2. H.C. Davey, D.J. MacKay, Low density parity check codes over GF (q), in: Information Theory Workshop, pp. 70-71, 1998.
  3. B. Zhou, J. Kang, S. Song, S. Lin, K. Abdel-Ghaffar, M. Xu, Construction of non-binary quasi-cyclic LDPC codes by arrays and array dispersions, IEEE Transactions on Communications, vol.57, pp.1652-1662, 2009. https://doi.org/10.1109/TCOMM.2009.06.070313
  4. V. Savin, Min-Max decoding for non binary LDPC codes, IEEE International Symposium on Information Theory (ISIT), pp. 960-964, 2008.
  5. F. Cai, Low-complexity Decoding Algorithms and Architectures for Non-binary LDPC Codes, Ph.D. thesis, Case Western Reserve University, 2013.
  6. L. Barnault, D. Declercq, Fast decoding algorithm for LDPC over GF ($2^q$), in: IEEE Information Theory Workshop, pp. 70-73, 2003.
  7. D. Declercq, M. Fossorier, Decoding algorithms for nonbinary LDPC codes over GF, IEEE Transactions on Communications, vol.55, pp.633-643, 2007. https://doi.org/10.1109/TCOMM.2007.894088
  8. X. Chen, S. Lin, V. Akella, Efficient configurable decoder architecture for nonbinary Quasi-Cyclic LDPC codes, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.59, pp.188-197, 2012. https://doi.org/10.1109/TCSI.2011.2161416
  9. C.-S. Choi, H. Lee, Block-Layered Decoder Architecture for Quasi-Cyclic Nonbinary LDPC Codes, Journal of Signal Processing Systems, vol.78, no.2, pp.209-222, Feb. 2015. https://doi.org/10.1007/s11265-013-0816-5
  10. X. Zhang, F. Cai, Efficient partial-parallel decoder architecture for quasi-cyclic nonbinary LDPC codes, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.58, pp.402-414, 2011. https://doi.org/10.1109/TCSI.2010.2071830
  11. D. Kirk, W. mei w. hwu, Programming Massively Parallel Processors: A Hands-on Approach, Burlington, MA, USA, 2010.
  12. S. Wang, S. Cheng, Q. Wu, A parallel decoding algorithm of LDPC codes using CUDA, in: Signals, systems and computers, 42nd asilomar conference on, pp. 171-175, 2008.
  13. G. Falcao, L. Sousa, V. Silva, Massive parallel LDPC decoding on GPU, in: Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming, pp. 83-90, 2008.
  14. Y. Zhao, X. Chen, C.-W. Sham, W.M. Tam, F.C. Lau, Efficient decoding of QC-LDPC codes using GPUs, in: International Conference on Algorithms and Architectures for Parallel Processing, Springer, pp. 294-305, 2011.
  15. G. Falcao, L. Sousa, V. Silva, Massively LDPC decoding on multicore architectures, IEEE Transactions on Parallel and Distributed Systems, vol.22, pp.309-322, 2011. https://doi.org/10.1109/TPDS.2010.66
  16. B. Le Gal, C. Jego, J. Crenne, A high throughput efficient approach for decoding LDPC codes onto GPU devices, IEEE Embedded Systems Letters, vol.6, pp.29-32, 2014. https://doi.org/10.1109/LES.2014.2311317
  17. J. Andrade, G. Falcao, V. Silva, K. Kasai, FFT-SPA non-binary LDPC decoding on GPU, in: IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), pp. 5099-5103, 2013.
  18. G. Wang, H. Shen, B. Yin, M. Wu, Y. Sun, J.R. Cavallaro, Parallel nonbinary LDPC decoding on GPU, in: Asilomar Conference on Signals, Systems and Computers (ASILOMAR), pp. 1277-1281, 2012.
  19. M. Beermann, E. Monro, L. Schmalen, P. Vary, High speed decoding of non-binary irregular LDPC codes using GPUs, in: IEEE Workshop on Signal Processing Systems (SiPS), pp. 36-41, 2013.
  20. M. Beermann, E. Monzo, L. Schmalen, P. Vary, GPU accelerated belief propagation decoding of non-binary LDPC codes with parallel and sequential scheduling, Journal of Signal Processing Systems, vol.78, pp.21-34, Jan. 2015. https://doi.org/10.1007/s11265-014-0927-7
  21. H. Song, J. Cruz, Reduced-complexity decoding of Q-ary LDPC codes for magnetic recording, IEEE Transactions on Magnetics, vol.39, pp.1081-1087, 2003. https://doi.org/10.1109/TMAG.2003.808600
  22. H. Wymeersch, H. Steendam, M. Moeneclaey, Log-domain decoding of LDPC codes over GF (q), in: IEEE International Conference on Communications, pp. 772-776, 2004.
  23. F. Cai, X. Zhang, Relaxed min-max decoder architectures for nonbinary low-density parity-check codes, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.21, no.11, pp.2010-2023, 2013. https://doi.org/10.1109/TVLSI.2012.2226920