Journal of the Korea Institute of Information and Communication Engineering (한국정보통신학회논문지)

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
권호 표지
DOI QR코드

DOI QR Code

VLSI Design of Parallel Scheme for Comparison of Multiple Digital Signals

다중 디지털 신호의 비교를 위한 병렬 기법의 VLSI 설계

  • Seo, Young-Ho (Ingenium College of Liberal Arts, Kwangwoon University) ;
  • Lee, Yong-Seok (Korea Electronics Technology Institute) ;
  • Kim, Dong-Wook (Department of Electronic Materials Engineering, Kwangwoon University)
  • Received : 2016.11.04
  • Accepted : 2016.12.12
  • Published : 2017.04.30
Download PDF
⟨ Previous Next ⟩

Abstract

This paper proposes a new algorithm for comparing amplitude between multiple digital input signals and its digital logic architecture. After simultaneously comparing multiple inputs, the proposed algorithm can provide the information of the largest (or smallest) value among them by using a simple digital logic function. The drawback of the method is to increase hardware resource. To overcome this we propose a reuse method of the overlapped logic operation. The proposed method focuses on enhancing the operational clock frequency, in other words decreasing combinational delay time. After implementing the comparing method with HDL (hardware description language), we experiment on it with environment of Cyclone III EP3C40F324A7 FPGA of Altera Inc. In case of 4 input signals, it can increase the operational speed as mush as 1.66 times with 1.20 times the hardware resource. In case of 8, it can also have 2.29 times the clock frequency and 2.15 times the hardware resource.

본 논문에서는 여러 디지털 신호의 크기를 비교하기 위한 알고리즘 및 디지털 회로를 제안한다. 제안하고자 하는 알고리즘은 여러 입력을 동시에 비교한 후에 간단한 디지털 논리 함수를 이용하여 그 입력들 중에서 가장 큰 값(혹은 가장 작은 값)을 검출하는 방법을 제공할 수 있다. 이 방식의 단점은 하드웨어 자원이 증가하는 것인데, 이를 위해 중복된 논리동작을 재사용하는 방법을 제안한다. 제안하고자 하는 방식은 회로 속도의 증가, 즉 지연시간의 감소에 초점을 맞추었다. 제안한 비교 알고리즘은 HDL로 구현한 후에 Altera사의 Cyclone III EP3C40F324A7 FPGA 환경에서 실험하였다. 4입력의 경우에 1.20배의 하드웨어 자원을 사용하면서 1.66배 만큼 동작 속도를 증가시킬 수 있다. 또한 8입력의 경우에는 2.15배의 하드웨어 자원을 사용하면서 2.29배로 동작 속도를 증가시킬 수 있다.

Keywords

References

  1. R. J. Tocci, N. Widmer, and G. Moss, Digital Systems: Principles and Applications, 11th ed. London, Pearson, 2010.
  2. I. Koren, Computer Arithmetic Algorithms, 2nd ed, Florida, A K Peters/CRC Press, 2001.
  3. K. Mehlhorn, Sorting and Searching, 1st ed. Springer- Verlag, Berlin, 1984.
  4. W. Alexander, C and M Williams, Digital Signal Processing: Principles, Algorithms and System Design, 1st ed, Massachusetts, Academic Press, 2017.
  5. J.W. Kang, "Disparity Vector Derivation Method for Texture-Video-First-Coding Modes of 3D Video Coding Standards," Journal of The Korean Institute of Communication Sciences, vol. 40. no. 10, pp. 2080-2089, Oct. 2015. https://doi.org/10.7840/kics.2015.40.10.2080
  6. S.B. Yoon, S.H. B, H.J. Park, and J.H. Yi, "Probabilistic Graph Based Object Category Recognition Using the Context of Object-Action Interaction," Journal of The Korean Institute of Communication Sciences, vol. 40, no. 11, pp. 2284-2290, Nov. 2015. https://doi.org/10.7840/kics.2015.40.11.2284
  7. H. Lee, K. Cho, H. Kim, S. Choi, J. Lim and J. Kim, "Electrical performance of high bandwidth memory (HBM) interposer channel in terabyte/s bandwidth graphics module," 2015 International 3D Systems Integration Conference (3DIC), Sendai, pp. TS2.2.1-TS2.2.4, 2015.
  8. M. K. Jaiswal, B. S. C. Varma, H. K. H. So, M. Balakrishnan, K. Paul, and R. C. C. Cheung, "Configurable Architectures for Multi-Mode Floating Point Adders," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, no. 8, pp. 2079-2090, Aug. 2015. https://doi.org/10.1109/TCSI.2015.2452351
  9. S. Abed, M. Al-Shayeji, S. Sultan, and N. Mohammad, "Hybrid approach based on partial tag comparison technique and search methods to improve cache performance," IET Computers & Digital Techniques, vol. 10, no. 2, pp. 69-76, Nov. 2016. https://doi.org/10.1049/iet-cdt.2015.0097
  10. M. Codish, L. Cruz-Filipe, M. Frank, and P. Schneider-Kamp, "Twenty-Five Comparators Is Optimal When Sorting Nine Inputs (and Twenty-Nine for Ten)," 2014 IEEE 26th International Conference on Tools with Artificial Intelligence, Limassol, pp. 186-193, 2014.
  11. R. Woo, S. Choi, J.H. Sohn, S.J. Song, and H.J. Yoo, "A Low-Power 3-D Rendering Engine With Two Texture Units and 29-Mb Embedded DRAM for 3G Multimedia Terminals," IEEE Journal of Solid-State Circuits, vol. 39, no.7, pp. 1101-1109, Jul. 2004. https://doi.org/10.1109/JSSC.2004.829406
  12. S. S. Ameer Abbas, S. J. Thiruvengadam, and N. A. R. Kumar, "Realization of receiver architectures using VLSI DSP techniques for broadcast channel in LTE," 2014 International Conference on Embedded Systems (ICES), Coimbatore, pp. 12-17, 2014.
  13. C.C. Wang, C.F. Wu, and K.C. Tsai, "1 GHz 64-Bit high-speed comparator using ANT dynamic logic with two-phase clocking," IEE Proceedings - Computers and Digital Techniques., vol. 145, no. 6, pp. 433-436, Nov. 1998. https://doi.org/10.1049/ip-cdt:19982348
  14. C.C. Wang, P.M. Lee, C.F. Wu, and H.L. Wu, "High Fan-In Dynamic CMOS Comparators With Low Transistor Count," IEEE Transactions on Circuits and Systems I : Fundamental Theory and Applications, vol. 50, issue 9, pp. 12161-220, Sep. 2003.
  15. C.H. Huang and J.S. Wang, "High-performance and power-efficient CMOS comparators," IEEE Journal of Solid-State Circuits, vol. 38, no. 2, pp. 254-262, Feb. 2003. https://doi.org/10.1109/JSSC.2002.807409
  16. S.W. Cheng, "A High-Speed Magnitude Comparator With Small Transistor Count," IEEE Proceedings of International Conference on Electronics, Circuits and Systems, vol. 3, pp. 1168-1171, Dec. 2003.
  17. H.M. Lam and C.Y. Tsui, "High-performance single clock cycle CMOS comparator," Electron. Letters., vol. 42, no. 2, pp. 75-77, Jan. 2006. https://doi.org/10.1049/el:20063083
  18. H.M. Lam and C.Y. Tsui, "A MUX-based high-performance single cycle CMOS comparator," IEEE Transactions on Circuits and Systems. II, Exp. Briefs, vol. 54, no. 7, pp. 591-595, Jul. 2007. https://doi.org/10.1109/TCSII.2007.899856
  19. J.Y. Kim and H.J. Yoo, "Bitwise Competition Logic for Compact Digital Comparator," IEEE Asian Solid Stated Circuits Conference, Jeju, pp. 59-62, Nov. 2007.
  20. S. Perri, and P. Corsonello, "Fast low-cost implementation of single-clock cycle binary comparator," IEEE Transactions on Circuits and Systems II, Exp. Briefs, vol. 55, no. 12, pp. 1239-1243, Dec. 2008. https://doi.org/10.1109/TCSII.2008.2008063
  21. F. Frustaci, S. Perri, M. Lanuzza, and P. Corsonello, "A new low-power high-speed single-clock-cycle binary comparator," Proceedings of 2010 IEEE International Symposium on Circuits and Systems, Paris, pp. 317-320, May 2010.
  22. S. Deb and S. Chaudhury, "High-speed comparator architectures for fast binary comparison," 2012 Third International Conference on Emerging Applications of Information Technology (EAIT), Kolkata, pp. 454-457, Nov. 2012.
  23. P. Chuang, D. Li, and M. Sachdev, "A Low-Power High-Performance Single-Cycle Tree-Based 64-Bit Binary Comparator," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 59, no. 2, pp. 108-112, Feb. 2012. https://doi.org/10.1109/TCSII.2011.2180110
  24. S.C. Hsia, "High-speed multi-input comparator," IEE Proceedings - Circuits, Devices and Systems, vol. 152, no. 3, pp. 210-214, Jun. 2005. https://doi.org/10.1049/ip-cds:20041174
  25. M. Kim, J. Y. Kim, and H. J. Yoo, "A 1.55ns 0.015 mm2 64-bit quad number comparator," 2009 International Symposium on VLSI Design, Automation and Test, Hsinchu, pp. 283-286, Apr. 2009.
  26. ARM information center. AMBA [Internet]. Available: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.set.amba/index.html.