Journal of Power Electronics

  • 제17권1호
  • /
  • Pages.115-126
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  • 2017
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  • 1598-2092(pISSN)
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  • 2093-4718(eISSN)
전력전자학회 (The Korean Institute of Power Electronics)
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An Improved Switching Topology for Single Phase Multilevel Inverter with Capacitor Voltage Balancing Technique

  • 투고 : 2016.06.07
  • 심사 : 2016.11.02
  • 발행 : 2017.01.20
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초록

This paper presents a new cascaded asymmetrical single phase multilevel converter with a reduced number of isolated DC sources and power semiconductor switches. The proposed inverter has only two H-bridges connected in cascade, one switching at a high frequency and the other switching at a low frequency. The Low Switching Frequency Inverter (LSFI) generates seven levels whereas the High Switching Frequency Inverter (HSFI) generates only two levels. This paper also presents a solution to the capacitor balancing issues of the LSFI. The proposed inverter has lot of advantages such as reductions in the number of DC sources, switching losses, power electronic devices, size and cost. The proposed inverter with a capacitor voltage balancing algorithm is simulated using MATLAB/SIMULINK. The switching logic of the proposed inverter with a capacitor voltage balancing algorithm is developed using a FPGA SPATRAN 3A DSP board. A laboratory prototype is built to validate the simulation results.

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참고문헌

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피인용 문헌

  1. Evaluation of Impedance network Based 7-Level Switched Capacitor Multi Level Inverter for Single Phase Grid Integrated System pp.2250-2114, 2018, https://doi.org/10.1007/s40031-018-0348-2