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사인-선형 위상차 방식의 차동 양자화된 직접 디지털 주파수 합성기

The Differential Quantized Direct Digital Frequency Synthesizer Based on Sine-Linear Phase Difference

  • Kim, Chong-il (Catholic Kwandong University, Department of Electronic Engineering) ;
  • Lee, Hyun-seung (Department of Electronic Engineering Catholic Kwandong University) ;
  • Hong, Chan-ki (Catholic Kwandong University, Department of computer science)
  • 투고 : 2016.09.20
  • 심사 : 2016.09.22
  • 발행 : 2016.10.31

초록

본 논문에서는 sine-linear phase difference 방식과 DPCM 방식의 차동 양자화 기술을 응용하여 새로운 ROM 압축방식을 제안하고 이를 이용하여 저전력 직접 디지털 주파수 합성기를 FPGA를 사용하여 설계 및 제작한다. ROM 크기를 줄이기 위해 사인파의 1/4 주기를 $2^N$간격으로 표본화하여 양자화된 값을 양자화 ROM1에 저장하고 각 표본화 사이를 $2^K$간격으로 표본화하고 ROM1에 저장된 표본화 값의 차이를 ROM2에 저장하여 ROM의 크기를 줄이는 방식을 사용한다. 이를 사용함으로써 기존 방식 대비 약 37%의 ROM 크기만 필요하게 되여 전력 소모를 줄일 수 있다.

In this paper, a new method to reduce the size of ROM in the direct digital frequency synthesizer (DDFS) is proposed. This method use the sine-linear phase difference method and differential PCM. The new ROM compression method can reduce the ROM size by using the two ROM. The quantized value of sine-linear phase difference is saved by the ROM1 of the $2^N$ sample period. The ROM2 save the difference between the original sine-linear phase difference value and the saved sample value of the ROM1. The ROM compression ratio of 37% is achieved by this method. Also, the power consumption is decreased according to the ROM size reduction.

키워드

참고문헌

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