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Design of a Inverter-Based 3rd Order ΔΣ Modulator Using 1.5bit Comparators

1.5비트 비교기를 이용한 인버터 기반 3차 델타-시그마 변조기

  • Received : 2016.01.27
  • Accepted : 2016.07.04
  • Published : 2016.07.25

Abstract

This paper describes the third order feedforward delta-sigma modulator with inverter-based integrators and a 1.5bit comparator for the application of audio signal processing. The proposed 3rd-order delta-sigma modulator is multi-bit structure using 1.5 bit comparator instead of operational amplifier. This delta-sigma modulator has high SNR compared with single-bit 4th-order delta-sigma modulator in a low OSR. And it minimizes power consumes and simplified circuit structure using inverter-based integrator and using inverter-based integrator as analogue adder. The modulator was designed with 0.18um CMOS standard process and total chip area is $0.36mm^2$. The measured power cosumption is 28.8uW in a 0.8V analog supply and 66.6uW in a 1.8V digital supply. The measurement result shows that the peak SNDR of 80.7 dB, the ENOB of 13.1bit and the dynamic range of 86.1 dB with an input signal frequency of 2.5kHz, a sampling frequency of 2.56MHz and an oversampling rate of 64. The FOM (Walden) from the measurement result is 269 fJ/step, FOM (Schreier) was calculated as 169.3 dB.

본 논문에서는 음성 신호의 디지털 데이타 변환을 위한 인버터와 1.5비트 비교기를 이용한 CMOS 3차 델타-시그마 변조기를 설계하였다. 제안하는 3차 델타-시그마 변환기는 연산증폭기 대신에 1.5비트 비교기를 이용한 멀티비트 구조로 낮은 OSR에서 단일비트 4차 델타-시그마 변조기 대비 높은 신호대 잡음비를 확보하고 인버터 기반 적분기를 사용하여 소모 전력을 최소화 시키며 인버터 기반 적분기 회로를 아날로그 덧셈기로 이용함으로써 전력소모를 감소시키고 회로구조를 단순화 시켰다. 제안한 델타-시그마 변조기는 0.18um CMOS 표준 공정을 통해 제작되었으며, 전체 칩면적은 $0.36mm^2$으로 설계되었다. 제작된 칩의 측정 결과 아날로그 회로는 공급전압 0.8V에서 $28.8{\mu}W$, 디지털 회로는 공급전압 1.8V에서 $66.6{\mu}W$로 총 $95.4{\mu}W$의 전력소모가 측정되었다. 델타-시그마 변조기의 동작주파수 2.56MHz, OSR 64배의 조건에서 2.5kHz의 입력 정현파 신호를 인가하였을 때 SNDR은 80.7 dB, 유효비트수는 13.1 비트, 동적범위는 86.1 dB로 측정되었다. 측정결과로부터 FOM(Walden)은 269 fJ/step, FOM(Schreier)는 169.3 dB로 계산되었다.

Keywords

References

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