전자공학회논문지 (Journal of the Institute of Electronics and Information Engineers)

  • 제53권4호
  • /
  • Pages.68-75
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  • 2016
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  • 2287-5026(pISSN)
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  • 2288-159X(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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버스 프로토콜 호환 가능한 네트워크-온-칩에서의 분리된 주소/데이터 네트워크 설계

Separated Address/Data Network Design for Bus Protocol compatible Network-on-Chip

  • 정승아 (성균관대학교 정보통신대학) ;
  • 이재훈 (성균관대학교 정보통신대학) ;
  • 김상헌 (성균관대학교 정보통신대학) ;
  • 이재성 (성균관대학교 정보통신대학) ;
  • 한태희 (성균관대학교 정보통신대학)
  • Chung, Seungh Ah (College of Information & Communication Engineering, Sungkyunkwan University) ;
  • Lee, Jae Hoon (College of Information & Communication Engineering, Sungkyunkwan University) ;
  • Kim, Sang Heon (College of Information & Communication Engineering, Sungkyunkwan University) ;
  • Lee, Jae Sung (College of Information & Communication Engineering, Sungkyunkwan University) ;
  • Han, Tae Hee (College of Information & Communication Engineering, Sungkyunkwan University)
  • 투고 : 2016.02.02
  • 심사 : 2016.04.04
  • 발행 : 2016.04.25
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초록

다중 프로세서 시스템-온-칩(Multi-Processor SoC, MPSoC)에서의 코어 및 IP 개수 증가 추세에 따라 병렬처리와 확장성에 유리한 인터커넥션 구조인 네트워크-온-칩(Network-on-Chip, NoC)이 등장하였다. 하지만 기존 IP를 재활용하기 위해서는 버스 프로토콜과 호환가능한 NoC에서의 지연시간을 최적화하기 위한 연구가 필요하다. 본 논문에서는 버스 프로토콜 호환 가능한 NoC 설계 시, 버스 프로토콜에서 특성이 다른 다수의 트랜잭션 단계에서 유발되는 홉 수와 경로 충돌의 대립관계로 인해 지연시간이 증가하는 문제를 주소 및 데이터 네트워크로 분리 설계함으로써 해결하였다. 모의실험으로 벤치마크 어플리케이션과 무작위 생성한 어플리케이션에서의 실험 결과를 통해 Mesh구조와 TopGen의 비정형 토폴로지와 비교했을 때, 평균 지연시간은 19.46% 및 실행시간은 10.55% 감소하였다.

As the number of cores and IPs increase in multiprocessor system-on-chip (MPSoC), network-on-chip (NoC) has emerged as a promising novel interconnection architecture for its parallelism and scalability. However, minimization of the latency in NoC with legacy bus IPs must be addressed. In this paper, we focus on the latency minimization problem in NoC which accommodates legacy bus protocol based IPs considering the trade-offs between hop counts and path collisions. To resolve this problem, we propose separated address/data network for independent address and data phases of bus protocol. Compared to Mesh and irregular topologies generated by TopGen, experimental results show that average latency and execution time are reduced by 19.46% and 10.55%, respectively.

키워드

참고문헌

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