Digitally Current Controlled DC-DC Switching Converters Using an Adjacent Cycle Sampling Strategy

Abstract

A novel digital current control strategy for digitally controlled DC-DC switching converters, referred to as Adjacent Cycle Sampling (ACS), is proposed in this paper. For the ACS current control strategy, the available time interval from sampling the current to updating the duty ratio, is approximately one switching cycle. In addition, it is independent of the duty ratio. As a result, the contradiction between the processing speed of the hardware and the transient response speed can be effectively relaxed by using the ACS current control strategy. For digitally controlled buck DC-DC switching converters with trailing-edge modulation, digital current control algorithms with the ACS control strategy are derived for three different control objectives. These objectives are the valley, average, and peak inductor currents. In addition, the sub-harmonic oscillations of the above current control algorithms are analyzed and eliminated by using the digital slope compensation (DSC) method. Experimental results based on a FPGA are given, which verify the theoretical analysis results very well. It can be concluded that the ACS control has a faster transient response speed than the time delay control, and that its requirements for hardware processing speed can be reduced when compared with the deadbeat control. Therefore, it promises to be one of the key technologies for high-frequency DC-DC switching converters.

I. INTRODUCTION

On account of its obvious advantages, such as the flexibility to implement complicated control strategies and algorithms, the programmability to realize reconfigurable power systems, faster design process, high power conversion efficiency, robustness to noise, and insensitivity to parameter drifts of components, the digitally controlled DC-DC switching converter has gained a great deal of attention in the fields of power electronics and integrated circuits [1]-[20]. In order to improve the transient response features and to reduce the sizes of the passive filter components (inductor and capacitor), the switching frequency of the DC-DC converter is ever-increased. It is now up to several megahertz (the switching cycle is decreased to several hundred nanoseconds) [3], [4], which makes the available time interval for a digital control loop more critical. As a result, the hardware circuits must have higher processing speeds, which presents great challenges in the design and hardware implementation of digitally controlled high-frequency DC-DC switching converters [5].

It is well known that the transient response performances of a DC-DC switching converter can be effectively improved by adding a current controlled loop (often referred to as an inner loop) on the voltage controlled loop (often referred to as an outer loop) [3]-[5], [11]-[15]. The current controlled loop is based on the ripple of the inductor current. Most current control algorithms make the valley, peak, or average values [6-10] of the inductor current follow a reference signal generated by the outer voltage controlled loop. Depending on the response speed for variations of the inductor current, digital current control strategies can be classified as either deadbeat control [11], [12] or time delay control [13]-[15]. Although the deadbeat control has a fast response speed to variations of the output load, it requires a fast feedback loop processing speed since the available time interval for calculating and updating the duty ratio is less than one switching cycle. This is especially critical in the situation of a small duty ratio for trailing-edge and triangle trailing-edge modulations, and in the situation of a large duty ratio for leading-edge and triangle leading-edge modulations. On the other hand, for the time delay control, the available time interval is increased by one switching cycle when compared with the deadbeat control. This can ensure sufficient time for the calculation and renewal of the duty ratio which in turn relaxes the requirements for the processing speed of the hardware circuits. However, the transient response feature [16], [17] is degraded. Consequently, it is difficult to satisfy the requirements of digitally controlled high-frequency DC-DC switching converters by using the existing digital current control strategies.

In order to relax the contradiction between the processing speed (related to the cost) of hardware circuits and the transient response features, a novel digital current control strategy, referred to as Adjacent Cycle Sampling (ACS), is proposed and studied in this paper. Without a loss of generality, a buck DC-DC switching converter with trailing-edge modulation is taken as an example. Based on the proposed ACS control strategy, the current control algorithms for different control objectives are derived, and their stabilities are investigated. In addition, the elimination method of sub-harmonic oscillation is studied. Finally experimental results are given to verify the theoretical analysis.

The structure of this paper is as follows. In section II, the Adjacent Cycle Sampling (ACS) strategy is proposed after the analysis of the traditional current control strategies. In section III, a digital current control algorithms using the ACS control strategy is derived, where the valley, peak, and average values of the inductor current are used as control objectives. In section IV, sub-harmonic oscillations of the above current control algorithms are investigated and an elimination method is studied. In Section V, experimental results are provided to verify the theoretical analysis. Some conclusions are given in section VI.

 

II. ADJACENT CYCLE SAMPLING CURRENT CONTROL STRATEGY

Fig. 1 shows the configuration of a digitally current controlled buck DC-DC switching converter. It consists of two analog-to-digital converters (ADCv and ADCi are used to digitize the output voltage and inductor current, respectively), a digital compensator (including a current controller and a voltage controller), and a digital pulse-width modulator (DPWM). The digital control strategy and algorithm are implemented by the digital compensator. DPWM is used for the conversion of the digital duty ratio to an analog pulse signal. In this paper, a digital current control algorithm using the ACS control strategy is implemented by a current controller. In addition, a digital voltage control algorithm using PID (Proportion-Integration-Differentiation) is implemented by the voltage controller.

Fig. 1.Digitally current controlled DC-DC switching converter.

As shown in Fig. 1, VG and VO are the input and output voltages, respectively; VREF[n] is the digital value of the reference voltage, e[n] is the digital error between the output and reference voltages; iL is the current flowing through the inductor L; iREF[n] is the target reference generated by the voltage controller in the outer loop; d[n] is the digital duty ratio from the output of the digital compensator; and δ(t) is the analog pulse signal converted by the DPWM from d[n], the duty ratio of which is proportional to d[n]. The pulse signal δ(t) turns the power switches, S1 and S2, on or off to regulate the output voltage. C is the output filter capacitor, and R is the equivalent load resistor.

A. Traditional Current Control Strategies

Without a loss of generality, a DC-DC switching converter with trailing-edge modulation is considered only. Timing diagrams of the three current control strategies, deadbeat control (a), time delay control (b), and ACS control (c), are illustrated in Fig. 2, where Ts is the switching cycle, and d[n] is the duty ratio of the nth switching cycle, the value of which is between 0 and 1. Td is the available time interval for updating the duty ratio, including the time needed for the ADC’s conversion, the compensator’s algorithm calculation and the DPWM’s conversion.

Fig. 2.Timing diagrams of current control strategies: (a) Deadbeat control, (b) Time delay control, (c) ACS control, and (d) Analog pulse signal δ(t).

Fig. 2 (a) shows a timing diagram of the deadbeat control strategy. At the beginning of the nth cycle, or at the end of (n-1)th cycle, the inductor current, iL[n-1], is sampled. Then the duty ratio d[n] is calculated and updated within the nth cycle. For the deadbeat control strategy, Td is equal to d[n]Ts, namely the calculating and updating of the duty ratio should be completed within d[n]Ts, which is always less than one switching cycle. In addition, with a decrease of d[n] and/or Ts, Td becomes too little to finish the above operations unless the feedback loop has an extremely fast processing speed.

A timing diagram of the time delay control strategy is shown in Fig. 2 (b). The inductor current at the end of the (n-2)th cycle, iL[n-2], is sampled. Then the duty ratio d[n] is calculated and updated within the nth cycle. The available time interval Td, from sampling the inductor current to updating the duty ratio, is equal to (1+d[n])Ts, which is always larger than one switching cycle. As a result, although the requirement for the loop processing speed can be reduced, the transient response speed is degraded.

B. Adjacent Cycle Sampling Strategy

As shown in Fig. 2 (a), for the deadbeat control, there is some idle time for the hardware circuits in every cycle. The basic idea of the Adjacent Cycle Sampling (ACS) control strategy is to utilize the idle time of the hardware circuits during the previous cycle. This is done to calculate the duty ratio of the present cycle.

Fig. 2(c) shows a timing diagram of the ACS control strategy. The inductor current of the previous cycle, iL[n-1], is sampled at the falling edge of the pulse signal δ(t) (here for trailing-edge modulation). Then the duty ratio d[n] is calculated and updated based on iL[n-1]. Therefore, the available time interval Td is composed of two items: the switch off period of the previous cycle (the idle time of the hardware circuit in the deadbeat control), (1-d[n-1])Ts, and the switch on period of the present cycle, d[n]Ts. Thus, Td can be expressed as:

Since the two adjacent switching cycles have almost the same duty ratio, namely d[n-1]≈d[n], (1) can be rewritten as:

It can be concluded that, for the ACS control strategy, the available time interval is approximately equal to one switching cycle. In addition, it is independent of the duty ratio d[n]. Therefore, it can be predicted that, the ACS control has a faster transient response speed than the time delay control, and its requirement for the loop processing speed can be reduced when compared with the deadbeat control.

From Fig. 2, it can be observed that for all three kinds of current control strategies, the deadbeat, time delay and ACS control, the sampling time point of the inductor current is located at the beginning of the present cycle, at the end of two cycle before the present cycle, and the falling edge of previous cycle, respectively. Since the ACS control samples the inductor current at a certain point of the adjacent previous cycle, it is referred to as Adjacent Cycle Sampling control.

For a comparison of the above three current control strategies, the available time intervals for calculating and updating the duty ratio are summarized in TABLE I. In addition to the trailing-edge modulation, three other kinds of modulation (leading-edge, trailing-triangle, and leading-triangle) are also included for reference, without verbose analysis.

TABLE IAVAILABLE TIME INTERVAL FOR CALCULATING AND UPDATING THE DUTY RATIO

From TABLE I, it can be observed that, the available time intervals of the deadbeat, ACS and time delay control strategies are less than, approximately equal to, and larger than one switching cycle, respectively. The ACS control strategy is especially suitable for high-frequency DC-DC switching converters owing to its almost constant available time interval.

It should be noted that when duty ratio d[n] gets smaller and smaller, the time interval reserved for the time delay control is approximately equal to one switching period, Ts. This is almost the same as that for the proposed ACS method. However, a transient performance difference between the two methods still exists since their sampling points are different. As shown in Fig. 2, the sampling point of the proposed ACS method is more close to the updating point than that of the time delay control. Therefore, the value of the inductor current estimated by the ACS control law is closer to the actual value of the inductor current when compared with the time delay control.

 

III. ACS CURRENT CONTROL ALGORITHMS

Fig. 3 shows waveforms of the inductor current and the reference current when the ACS control strategy is used and the valley inductor current is taken as the control objective, where the buck DC-DC switching converter has trailing-edge modulation and works in the continuous conduction mode (CCM). ip and iv represent the peak and valley values of the inductor current, respectively.

Fig. 3.ACS control strategy for valley inductor current control.

For the buck DC-DC switching converter shown in Fig. 1, the rising and falling slopes of the inductor current ripples, m1 and m2, as shown in Fig. 3, are given as follows.

By utilizing the above rising and falling slopes, and the sampling values of the inductor current and reference current at the falling edge of δ(t) in the previous cycle, it is possible to establish the digital current control algorithms when using the ACS control strategy, for the control objectives of valley, average, and peak inductor currents, respectively.

A. The Valley Current Control Algorithm

The valley current control principle is shown in Fig. 3. In order to control the inductor current to follow the reference current, the valley value of the inductor current in the nth cycle should be equal to the sampling value of the reference current in the (n-1)th cycle. Thus, the following is obtained:

From Fig. 3, iv[n] can be calculated as:

For the ACS control, since the peak value of the inductor current in the (n-1)th cycle, ip[n-1], is sampled, it is necessary to express iv[n-1] in (5) by ip[n-1]. From Fig. 3, the following relationship between iv[n-1] and ip[n-1] can be obtained:

By substituting (6) into (5), iv[n]can be expressed as:

By substituting (7) into (4) and rearranging the equation, it is possible to obtain the valley current control algorithm as shown in (8).

B. The Average Current Control Algorithm

Fig. 4 shows the ACS control strategy for the average current control, where in order to control the inductor current to follow the reference current, the average value of the inductor current in the nth cycle is impelled to be equal to the sampling value of the reference current in the (n-1)th cycle.

Fig. 4.ACS control strategy for average inductor current control.

Thus, the following equation is obtained:

Due to the fact that the inductor current is different during switch on and switch off, the average value of the inductor current in the nth cycle can be calculated based on the subsection integral. Thus, the average value of the inductor current is obtained as:

The second-order term about d[n] in (10) makes the current control algorithm become complex and difficult to implement by the compensator. Therefore, it is necessary to replace it by other parameters. The ratio of the input and output voltages in the steady-state can be substituted for (d[n])2 in (10). In addition, by using (3), (d[n])2 can be expressed as:

By substituting (11) into (10), it is possible to obtain the expression of the average inductor current as shown in (12).

According to (9) and (12), the average current control algorithm can be derived as shown in (13).

C. The Peak Current Control Algorithm

Fig. 5 shows the ACS control strategy for the peak current control, where the peak value of the inductor current in the nth cycle is impelled to be equal to the sampling value of the reference current in the (n-1)th cycle.

Fig. 5.ACS control strategy for peak inductor current control.

Thus, the following equation is obtained:

The peak value of the inductor current can be calculated by the following equation:

By merging (14) and (15), it is easy to obtain the peak current control algorithm as shown in (16).

So far, the current control algorithms for the three control objectives have been derived for the valley, average, and peak inductor currents, respectively. It is noteworthy that the three current control algorithms have a uniform format in which the duty ratio in the nth cycle can be expressed by a linear combination of the reference current and the peak inductor current in the (n-1)th cycle. Therefore, for a buck DC-DC switching converter with trailing-edge modulation, the current control algorithms with the ACS control strategy can be expressed by the uniform format as shown in (17).

In (17), K1 is the accumulation factor, which reflects the accumulative effect of the duty ratio of the previous cycle onto that of the present cycle; K2 is the error coefficient, which reflects the impact of the error between the sampled inductor current and the reference current onto the duty ratio of the present cycle; and K3 is the offset factor. Here, for the buck DC-DC switching converter with trailing-edge modulation, the control coefficients of the current control algorithms, using the ACS control, K1, K2 , and K3 , are summarized in TABLE II.

TABLE IITHE CONTROL COEFFICIENTS OF CURRENT CONTROL LAWS USING ACS CONTROL

 

IV. ANALYSIS AND ELIMINATION OF SUB-HARMONIC OSCILLATION

It is well known that sub-harmonic oscillations may occur in digitally controlled DC-DC switching converters [18-20]. Therefore, it is necessary to investigate the stabilities of above current control algorithms, where the ACS control strategy is used.

A. Analysis of Sub-Harmonic Oscillation

Since the loop bandwidth of a buck DC-DC switching converter is far less than the switching frequency, both the slopes of the inductor current ripple, shown in (3), and the reference current are assumed to be constant in the following analysis.

Fig. 6 shows the mechanism of sub-harmonic oscillations for the ACS peak current control with trailing-edge modulation, where the solid line indicates the steady-state inductor current waveform, and the dotted line shows the inductor current waveform when a perturbation in the peak value, ∆ip[n-1], is added to the steady-state value at the time point of d[n-1]Ts.

Fig. 6.Sub-harmonic oscillation for the ACS peak current control with trailing-edge modulation.

According to Fig. 6, the signal value with perturbations is equal to the steady-state value plus a perturbing quantity. Therefore, the following equations can be written:

Here, IP, IV and D are the steady-state values of the peak inductor current, valley inductor current and duty ratio, while ∆d[n] and ∆iv[n] are the perturbing-quantities of the duty ratio and valley inductor current in the present cycle, respectively.

It is reasonable to consider that the perturbation of the peak current ∆ip[n-1], which appeared at the time point of d[n-1]Ts, does not affect the duty ratio in the (n-1)th cycle. Therefore, the following relation is obtained:

Then, by substituting (18) and (19) into (16), and using IREF to replace the reference current, the current control algorithm shown in (16) can be rewritten as:

By eliminating the steady-state values in (20), it is possible to obtain the perturbing-quantity of the duty ratio of the nth cycle, ∆d[n], as shown in (21).

Furthermore, by substituting (18) and (19) into (7) and (21), the relationships between perturbing-quantities of ∆d[n], ∆iv[n] and ∆ip[n-1] can be obtained as:

Then, from (23), the transmissibility of the perturbation η can be derived as:

If the absolute value of η is less than 1, the current control algorithm is stable, and hence no sub-harmonic oscillation phenomena can occur. Thus, according to (24), it can be concluded that perturbations of the inductor current do not lead to sub-harmonic oscillations when the duty ratio does not exceed 0.5 for the ACS peak current control with trailing-edge modulation.

For the ACS valley and average current control algorithms, it is possible to adopt an analysis process similar to the one above to investigate their stabilities. Here only the analysis results are given. The perturbing-quantity of the duty ratio is the same for both the valley and average current control algorithms, as shown in (25).

By merging (22) and (25), it is possible to come to the conclusion that both the perturbing-quantity of the inductor current, ∆iv[n], and the transmissibility of the perturbation, η, are equal to zero. This indicates that for the ACS valley and average current control algorithms, perturbations of the inductor current will not lead to sub-harmonic oscillations for any duty ratio.

B. Elimination of Sub-harmonic Oscillations

In this paper, the digital slope compensation (DSC) method [19], [20] is used to eliminate the sub-harmonic oscillations for the ACS peak current control. As shown in Fig. 7, after the DSC is applied to the reference current, during one switching cycle, the reference current iREF is no longer a constant value, but is a falling straight line with a slope of –ma (dashed–dotted line).

Fig. 7.Elimination of the sub-harmonic oscillation for ACS peak current control with DSC.

The control relation for the ACS peak current control with the DSC is changed. It can be expressed as:

Based on (26), it is possible to obtain a new ACS peak current control algorithm by using the derivations in section III. C. This is shown in (27).

Furthermore, for the new ACS peak current control algorithm with the DSC, it is possible to derive new expressions for both the perturbing-quantity of the inductor current and the transmissibility of the perturbation by using the derivations in section IV. These are shown as follows:

In order to eliminate sub-harmonic oscillations, the absolute value of η should be less than 1. From (29) it can be seen that the compensation slope ma must satisfy the following condition:

Equations (16) and (27) show the ACS peak current control algorithms without the DSC and with the DSC. By comparing (27) with (16), it can be seen that whether the DSC is used or not, the ACS peak current control algorithms are in the uniform format. Therefore, the ACS peak current control algorithm with the DSC can be obtained only by changing the control coefficients of (16) into those of (27). Therefore, there is no need to add any extra slope compensation hardware circuit.

As illustrated in Fig. 7, if the DSC is used and the slope ma is satisfied with (30), the perturbation of the valley current in the present cycle, ∆iv[n], is less than that of the peak current in the previous cycle, ∆ip[n-1]. Therefore, the perturbation of the inductor current will gradually disappear and eventually recover to its steady-state value. Thus, the sub-harmonic oscillation is eliminated.

 

V. EXPERIMENT RESULTS

To verify the above theoretical analysis of the ACS current control strategies and algorithms, some experiments are carried out using a hardware platform that is based on the structure shown in Fig. 1. In this platform, the digital compensator is implemented by a field programmable gate array (FPGA) from Altera. In addition, the load current is generated by an electronic load instrument N3300A from Agilent. Furthermore, a 9-bit ADCi for sampling the inductor current, an 8-bit ADCv for sampling the output voltage, and an 11-bit DPWM for converting the digital duty ratio into an analog pulse signal, are also used. A buck DC-DC switching converter with trailing-edge modulation operates in the continuous conduction mode (CCM), and the circuit parameters of the power stage are chosen as: VG=5.0 V, L =2.2 μH, C=2.2 μF, R=2 Ω, and the switching cycle=1 MHz (Ts=1 μs).

The experimental conditions are divided into two cases, 1) case I: duty ratio D=0.36, output voltage VO=1.8 V, and load current IL=0.9 A; and 2) case II: D=0.6, VO=3.0 V, and IL=1.5 A, while the other circuit parameters are same in both cases as defined above.

Fig. 8 shows the transient response features when the load current is step-changed from 1.9 A to 0.9 A. Here, the ACS current control strategy is used for the three control objectives of valley, peak, and average currents, and the experiment conditions are case I (D=0.36 and VO=1.8 V). The control coefficients of the current control law for the three current control objectives are summarized in TABLE III.

Fig. 8Transient response features of ACS current control strategies for: (a) Valley current control, (b) Peak current control, and (c) Average current control.

TABLE IIICONTROL COEFFICIENTS OF CURRENT CONTROL LAW FOR THREE CONTROL OBJECTIVES

Fig. 9 shows the amplitude and phase-frequency characteristics of the outer loop gain. The control bandwidth is 100 KHz which is equal to one tenth of the switching frequency, and the phase margin is 83.9 degrees. Fig. 10 and Fig. 11 show the amplitude and phase-frequency characteristics of the inner loop gain for the current control using MATLAB and PSIM simulations, respectively. It can be seen that the results of the two simulation match very well, especially in the low-frequency region. This demonstrates the accuracy of the derived model of the current control laws. Since the experiments for the three control objectives are all based on the same outer loop gain and inner loop gain, the above comparison is fair.

Fig. 9.Amplitude- and phase-frequency characteristics of the outer loop gain.

Fig. 10.Amplitude- and phase-frequency characteristics of the inner loop gain for current control simulated by MATLAB.

Fig. 11.Amplitude- and phase-frequency characteristics of the inner loop gain for current control simulated by PSIM.

It can be seen that, the ACS current control algorithms are all stable, and that the system can generate a well-regulated output voltage. For the transient response features, no overshoot is observed for all three of the control objectives. The transition time, Ts, and the fluctuation voltage, ∆v, are summarized in TABLE IV. It can be seen that there is no significant difference in the transient response features for the three control objectives.

TABLE IVTRANSIENT RESPONSE OF OUTPUT VOLTAGE WITH ΔI=1A

Fig. 12 (a) and (b) show waveforms of the steady-state output voltage and inductor current using the ACS peak current control, both without and with the DSC, respectively. Here, the experiment condition is case II (D=0.6, VO=3.0 V, and IL=1.5 A).

Fig. 12.Steady-state output voltage and inductor current using ACS peak current control: (a) without DSC and (b) with DSC.

From Fig. 12 (a), it can be observed that in the situation of D=0.6 (D>0.5) and without the DSC, sub-harmonic oscillations occur. As a result, both the output voltage and inductor current are not regulated. However, by using the DSC with ma=0.75m2, the sub-harmonic oscillations can be eliminated completely as shown in Fig. 12 (b). The above experimental results verify the sub-harmonic oscillation eliminating method given in section IV.

In order to compare the proposed ACS current control strategy with the traditional deadbeat and time delay current control strategies, the transient response features while using the three current control strategies are measured and compared. Here, the duty ratio is equal to 0.36, and the control objective is the peak value of the inductor current. Fig. 13 shows the measured output voltage and inductor current when the load current is step-changed from 0.9 A to 2.4 A and then back to 0.9 A after 1 ms, where L1, L2, and L3 represent the ACS, deadbeat and time delay current control methods, respectively. From the enlarged waveforms in Fig. 13, it can be observed that, L1 nearly overlaps with L2, but that L3 is obviously delayed compared with L1 and L2. The transition times of L1, L2 and L3 are 60 μs, 60 μs and 87 μs, respectively. The above experimental results show that the transient response features of the ACS current control are significantly better than those of the time delay current control and the deadbeat current control. This is in accordance with the above theoretical analysis.

Fig. 13.Measured output voltage and inductor current when using ACS, deadbeat and time delay current control.

It is worth pointing out that since the hardware circuits used in the above experiments have very fast processing speeds, and the duty ratio is relatively large (D=0.36), for the deadbeat current control, calculating and updating the duty ratio can be finished in the present cycle. Therefore, the deadbeat current control has almost same transient response features as the ACS current control. However, with the decrease of the duty ratio and/or the increase of the switching frequency, the transient response features using the deadbeat current control may be degraded unless the processing speed (and cost) of hardware circuit is further increased.

 

VI. CONCLUSION

In this paper, the Adjacent Cycle Sampling (ACS) current control strategy, applied for digitally controlled DC-DC switching converters, has been proposed. The available time interval of the ACS current control is approximately equal to one switching cycle. In addition, it is independent of the duty ratio. It was demonstrated by theoretical analysis and experimental results that the ACS control has a faster transient response speed than the time delay control, and that its requirement for loop processing speed can be reduced when compared with the deadbeat control.

A buck DC-DC switching converter with trailing-edge modulation was taken as an example. Digital current control algorithms using the ACS control strategy have been derived for the three control objectives of the valley, average, and peak inductor currents, respectively. The experimental results revealed that there is no significant difference in the transient response features for the three control objectives.

The sub-harmonic oscillations of the above current control algorithms were analyzed. For the ACS peak current control, sub-harmonic oscillations will occur when the duty ratio exceeds 0.5. However, for the ACS valley and average current controls, no sub-harmonic oscillations exit for any duty ratio. Sub-harmonic oscillations occurring in the ACS peak current control can be eliminated using the digital slope compensation (DSC) method, in which the compensation slope ma must satisfy 0.5m2≤ ma≤m2. The experimental results have verified the theoretical analysis very well.

In this paper, although the ACS digital current control algorithms have only been studied for buck DC-DC switching converters with trailing-edge modulation, the ACS current control strategy can be easily expanded to other structures of DC-DC switching converters, such as boost, buck-boost and multi-phase converters, or expanded to other modulation modes, such as leading-edge, trailing-triangle, and leading-triangle modulations.