IEIE Transactions on Smart Processing and Computing

대한전자공학회 (The Institute of Electronics and Information Engineers)
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Using DSP Algorithms for CRC in a CAN Controller

  • Juan, Ronnie O. Serfa (Department of Electronic Engineering, College of Engineering, Cheongju University) ;
  • Kim, Hi Seok (Department of Electronic Engineering, College of Engineering, Cheongju University)
  • 투고 : 2016.02.16
  • 심사 : 2016.02.24
  • 발행 : 2016.02.29
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초록

A controller area network (CAN) controller is an integral part of an electronic control unit, particularly in an advanced driver assistance system application, and its characteristics should always be advantageous in all aspects of functionality especially in real time application. The cost should be low, while maintaining the functionality and reliability of the technology. However, a CAN protocol implementing serial operation results in slow throughput, especially in a cyclical redundancy checking (CRC) unit. In this paper, digital signal processing (DSP) algorithms are implemented, namely pipelining, unfolding, and retiming the CAN controller in the CRC unit, particularly for the encoder and decoder sections. It must attain a feasible iteration bound, a critical path that is appropriate for a CAN system, and must obtain a superior design of a high-speed parallel circuit for the CRC unit in order to have a faster transmission rate. The source code for the encoder and decoder was formulated in the Verilog hardware description language.

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참고문헌

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